IEEE Design & Test

Issue 4 • Aug. 2015

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  • Front Cover

    Publication Year: 2015, Page(s): C1
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  • Cover 2

    Publication Year: 2015, Page(s): C2
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  • Masthead

    Publication Year: 2015, Page(s): 1
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  • Table of Contents

    Publication Year: 2015, Page(s): 2
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  • Departments [Table of Contents]

    Publication Year: 2015, Page(s): 3
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  • Advances in 3-D Integrated Circuits, Systems, and CAD Tools

    Publication Year: 2015, Page(s):4 - 5
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  • Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools

    Publication Year: 2015, Page(s):6 - 7
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  • Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities

    Publication Year: 2015, Page(s):8 - 22
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB) | HTML iconHTML

    Three-dimensional integration is a breakthrough technology that provides numerous benefits such as better performance, lower power consumption, and wide bandwidth by vertical interconnects and 3-D stacking. This paper presents an overview regarding the physical design and CAD tools suitable for 3-D integrated circuits. View full abstract»

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  • Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)

    Publication Year: 2015, Page(s):23 - 31
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2921 KB) | HTML iconHTML

    Two-and-a-half-dimensional integration enables high-density interdie connections with low cost. This paper presents a through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration. View full abstract»

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  • Heat Dissipation Capability of a Package-on-Package Embedded Wafer-Level Package

    Publication Year: 2015, Page(s):32 - 39
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1234 KB) | HTML iconHTML

    In this work, the thermal analysis is performed to investigate and improve the heat dissipation capability of the fan-out eWLP POP structure. The simulation scheme was validated with the available experimental results conducted previously by Hoe et al. [9]. The 3-D package studied is shown in Figure 1. The thermal performance of the initial POP structure is evaluated as the baseline case. Then, th... View full abstract»

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  • A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers

    Publication Year: 2015, Page(s):40 - 48
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1814 KB) | HTML iconHTML

    This paper proposes a design-for-test architecture for efficient testing of 3-D ICs. The DfT architecture supports multiple dies, test data compression, and embedded cores. Commercial EDA tools are used to implement the DfT architecture. View full abstract»

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  • A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller

    Publication Year: 2015, Page(s):1 - 10
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB) | HTML iconHTML

    This paper presents silicon interposer-based 2.5-D integration of core and memory chips. Utilization of the channels through TSVs and interposer routing between the core and memory chips is maximized by bandwidth balancing enabled by space-time multiplexing of the channels with core clustering. View full abstract»

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  • Hierarchical Test Integration Methodology for 3-D ICs

    Publication Year: 2015, Page(s):59 - 70
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2657 KB) | HTML iconHTML

    In this paper, we propose a hierarchical test integration method for 3-D ICs. The method can handle a die with logic cores and memory cores. In addition to handle the test controlling of a hierarchical 3-D IC, furthermore, it also can support the test controlling of a 3-D IC with multiple towers. For a 3-D IC, the hierarchical test integration method uses two types of 1149.1-based test interfaces ... View full abstract»

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  • 3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization

    Publication Year: 2015, Page(s):71 - 80
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1763 KB) | HTML iconHTML

    WIDE I/O DRAM is a promising 3-D memory architecture for low-power/highperformance computing. This paper proposes a new WIDE I/O DRAM architecture to reduce access latency and energy consumption at the same time, which shows the possibility of further optimization of the WIDE I/O DRAM architecture and the impact of TSV usage in the memory architecture on the performance and energy consumption. View full abstract»

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  • Open Access Publishing

    Publication Year: 2015, Page(s): 81
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  • CEDA Currents

    Publication Year: 2015, Page(s):82 - 83
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  • IEEE Proceedings

    Publication Year: 2015, Page(s): 84
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  • Test Technology TC Newsletter

    Publication Year: 2015, Page(s):85 - 86
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  • myIEEE

    Publication Year: 2015, Page(s): 87
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  • A 3-D Forward into the Past

    Publication Year: 2015, Page(s): 88
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  • Cover 3

    Publication Year: 2015, Page(s): C3
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  • Cover 4

    Publication Year: 2015, Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

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Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)