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IEEE Micro

Issue 3 • May-June 2015

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Displaying Results 1 - 25 of 28
  • [Front cover]

    Publication Year: 2015, Page(s): c1
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  • Table of contents

    Publication Year: 2015, Page(s): c2
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  • [Masthead]

    Publication Year: 2015, Page(s): 1
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  • The State of the Computer Architecture Field and Its Top Picks

    Publication Year: 2015, Page(s):2 - 4
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  • The 2014 Top Picks in Computer Architecture

    Publication Year: 2015, Page(s):5 - 9
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  • A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services

    Publication Year: 2015, Page(s):10 - 22
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2740 KB) | HTML iconHTML

    To advance datacenter capabilities beyond what commodity server designs can provide, the authors designed and built a composable, reconfigurable fabric to accelerate large-scale software services. Each instantiation of the fabric consists of a 6 x 8 2D torus of high-end field-programmable gate arrays (FPGAs) embedded into a half-rack of 48 servers. The authors deployed the reconfigurable fabric in... View full abstract»

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  • Focus on Your Job Search

    Publication Year: 2015, Page(s): 23
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  • A High-Throughput Neural Network Accelerator

    Publication Year: 2015, Page(s):24 - 32
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (999 KB) | HTML iconHTML

    The authors designed an accelerator architecture for large-scale neural networks, with an emphasis on the impact of memory on accelerator design, performance, and energy. In this article, they present a concrete design at 65 nm that can perform 496 16-bit fixed-point operations in parallel every 1.02 ns, that is, 452 gop/s, in a 3.02mm2, 485-mw footprint (excluding main memory accesses)... View full abstract»

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  • Cloud Computing

    Publication Year: 2015, Page(s): 33
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  • The Q100 Database Processing Unit

    Publication Year: 2015, Page(s):34 - 46
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2420 KB) | HTML iconHTML

    The Q100 uses hardware specialization to improve the energy efficiency of analytic database applications. The proposed accelerators are called database processing units. DPUs are analogous to GPUs, but where GPUs target graphics applications, DPUs target analytic database workloads. This article demonstrates a proof of concept design, called the Q100, which provides one to two orders of magnitude ... View full abstract»

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  • Conferences in the Palm of Your Hand

    Publication Year: 2015, Page(s): 47
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  • Race Logic: Abusing Hardware Race Conditions to Perform Useful Computation

    Publication Year: 2015, Page(s):48 - 57
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3627 KB) | HTML iconHTML

    This article proposes a novel computing approach, dubbed race logic, in which information, instead of being represented as logic levels (as in conventional logic), is represented as a timing delay. Under this new representation, computations are based on the observation of the relative propagation times of signals injected into the circuit (that is, the outcome of races). Race logic is especially ... View full abstract»

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  • The Aladdin Approach to Accelerator Design and Modeling

    Publication Year: 2015, Page(s):58 - 70
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3331 KB) | HTML iconHTML

    Hardware specialization, in the form of datapath and control circuitry customized to particular algorithms or applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerators relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and exp... View full abstract»

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  • Call for Papers

    Publication Year: 2015, Page(s): 71
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  • Verifying Correct Microarchitectural Enforcement of Memory Consistency Models

    Publication Year: 2015, Page(s):72 - 82
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1775 KB) | HTML iconHTML

    Memory consistency models define the rules and guarantees about the ordering and visibility of memory references on multithreaded CPUs and systems on chip. PipeCheck offers a methodology and automated tool for verifying that a particular microarchitecture correctly implements the consistency model required by its architectural specification. View full abstract»

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  • Stay connected

    Publication Year: 2015, Page(s): 83
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  • PVCoherence: Designing Flat Coherence Protocols for Scalable Verification

    Publication Year: 2015, Page(s):84 - 91
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB) | HTML iconHTML

    The goal of this work is to design cache coherence protocols with many cores such that they can be verified with existing verification methodologies. In particular, the authors focus on flat (nonhierarchical) coherence protocols using a mostly automated methodology based on parametric verification. They present design guidelines that, if followed by architects, enable parametric verification of pr... View full abstract»

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  • Sharing Incentives and Fair Division for Multiprocessors

    Publication Year: 2015, Page(s):92 - 100
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1422 KB) | HTML iconHTML

    The trend in datacenter computing is toward large, shared hardware platforms, which poses two challenges to architects: sharing fairly and sharing multiple resources. Drawing on economic game theory, the authors rethink fairness in computer architecture and propose Resource Elasticity Fairness to find fair allocations that ensure sharing incentives, envy-freeness, Pareto efficiency, and strategy p... View full abstract»

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  • Take the CS Library wherever you go!

    Publication Year: 2015, Page(s): 101
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  • Address Translation for Throughput-Oriented Accelerators

    Publication Year: 2015, Page(s):102 - 113
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1054 KB) | HTML iconHTML

    With processor vendors embracing hardware heterogeneity, providing low overhead hardware and software abstractions to support easy-to-use programming models is a critical problem. In this context, this work sets the foundation for designing memory management units (MMUs) for GPUs in CPU/GPU systems, the key mechanism necessary to support the increasingly important unified address space paradigm in... View full abstract»

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  • EOLE: Toward a Practical Implementation of Value Prediction

    Publication Year: 2015, Page(s):114 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1323 KB) | HTML iconHTML

    A new architecture, Early/Out-of-Order/Late Execution (EOLE), leverages value prediction to execute a significant number of instructions outside the out-of-order engine. This approach reduces the issue width, which is a major contributor to both out-of-order engine complexity and the register file port requirement. This reduction paves the way for a truly practical implementation of value predicti... View full abstract»

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  • Memory Persistency: Semantics for Byte-Addressable Nonvolatile Memory Technologies

    Publication Year: 2015, Page(s):125 - 131
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (311 KB) | HTML iconHTML

    Emerging nonvolatile memory technologies (NVRAM) promise the performance of DRAM with the persistence of disk. However, constraining the NVRAM write order, necessary to ensure recovery correctness, limits the NVRAM write concurrency and degrades throughput. New memory interfaces are required to efficiently describe write constraints and allow high-performance and high-concurrency data structures. ... View full abstract»

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  • Uncertain<T>: Abstractions for Uncertain Hardware and Software

    Publication Year: 2015, Page(s):132 - 143
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1364 KB) | HTML iconHTML

    Building correct, efficient systems that reason about the approximations produced by sensors, machine learning, big data, humans, and approximate hardware and software requires new standards and abstractions. The Uncertain <;T>; software abstraction aims to tackle these pervasive correctness, optimization, and programmability problems and guide hardware and software designers in producing es... View full abstract»

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  • Thoughts on Winning the 2014 Eckert-Mauchly Award

    Publication Year: 2015, Page(s):144 - 146
    Cited by:  Papers (1)
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  • Writing Well

    Publication Year: 2015, Page(s):147 - 149
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Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center