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Computers, IEEE Transactions on

Issue 6 • Date June 1994

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Displaying Results 1 - 15 of 15
  • Comments on "Distributed algorithms for network recognition problems"

    Publication Year: 1994
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (90 KB)

    K.V.S. Ramarao (1989) proposed distributed algorithms to recognize five network topologies. In these comments, we first use a counter example to comment that the approach by Ramarao of recognizing a star topology is incomplete. Then, we propose two modified approaches to do the work.<> View full abstract»

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  • On bends and distances of paths among obstacles in two-layer interconnection model

    Publication Year: 1994, Page(s):711 - 724
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1408 KB)

    We consider problems of finding assorted rectilinear paths among rectilinear obstacles in a two-layer interconnection model according to the number of bends and the 1-layer distance (y-distance). Using a horizontal wave-front approach, optimal θ(e log e) time algorithms are presented to find the shortest path and the minimum-bend path using linear space, and to find the shortest minimum-bend... View full abstract»

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  • A comparison of trace-sampling techniques for multi-megabyte caches

    Publication Year: 1994, Page(s):664 - 675
    Cited by:  Papers (35)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1240 KB)

    The paper compares the trace-sampling techniques of set sampling and time sampling. Using the multi-billion reference traces of A. Borg et al. (1990), we apply both techniques to multi-megabyte caches, where sampling is most valuable. We evaluate whether either technique meets a 10% sampling goal: a method meets this goal if, at least 90% of the time, it estimates the trace's true misses per instr... View full abstract»

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  • Construction of check sets for algorithm-based fault tolerance

    Publication Year: 1994, Page(s):641 - 650
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    Algorithm-based fault tolerance (ABFT) is a popular approach to achieve fault and error detection in multiprocessor systems. The design problem for ABFT is concerned with the construction of a check set of minimum cardinality that detects a specified number of errors or faults. Previous work on this problem has assumed an a priori bound on the size of a check. We motivate and carry out an investig... View full abstract»

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  • The derivation and experimental verification of clock synchronization theory

    Publication Year: 1994, Page(s):676 - 686
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    The objective of this work is to validate mathematically derived clock synchronization theories and their associated algorithms through experiment. Two theories are considered, the Interactive Convergence Clock Synchronization Algorithm and the Mid-Point Algorithm. Special clock circuitry was designed and built so that several operating conditions and failure modes (including malicious failures) c... View full abstract»

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  • On the genus of star graphs

    Publication Year: 1994, Page(s):755 - 759
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    The star graph has recently been suggested as an alternative to the hypercube. The star graph has a rich structure and symmetry properties as well as desirable fault-tolerant characteristics. The star graph's maximum vertex degree and diameter, viewed as functions of network size, grow less rapidly than the corresponding measures in a hypercube. We investigate the genus of the star graph and compa... View full abstract»

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  • Some characterizations of functions computable in on-line arithmetic

    Publication Year: 1994, Page(s):752 - 755
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    After a short introduction to on-line computing, we prove that the functions computable in on-line by a finite automaton are piecewise affine functions whose coefficients are rational numbers (i.e., the functions f(x)=ax+b, or f(x,y)=ax+by+c where a, b, and c are rational). A consequence of this study is that multiplication, division and elementary functions of operands of arbitrarily long length ... View full abstract»

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  • Information dissemination in distributed systems with faulty units

    Publication Year: 1994, Page(s):698 - 710
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1308 KB)

    Consider a network consisting of units connected by links in which some units could be faulty. Suppose each unit has a message which must be transmitted to all other (fault-free) units. We present an algorithm for doing this in a network operating in a fully distributed manner that requires at most 3n logn+O(n) message transmissions by fault-free units. Among other things, our result can be used t... View full abstract»

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  • False sharing and spatial locality in multiprocessor caches

    Publication Year: 1994, Page(s):651 - 663
    Cited by:  Papers (44)  |  Patents (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1284 KB)

    The performance of the data cache in shared-memory multiprocessors has been shown to be different from that in uniprocessors. In particular, cache miss rates in multiprocessors do not show the sharp drop typical of uniprocessors when the size of the cache block increases. The resulting high cache miss rate is a cause of concern, since it can significantly limit the performance of multiprocessors. ... View full abstract»

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  • Hypergraph coloring and reconfigured RAM testing

    Publication Year: 1994, Page(s):725 - 736
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1184 KB)

    RAM decoders are designed with a view to minimize the overall silicon area and critical path lengths. This can result in designs in which-physically adjacent rows (and columns) are not logically adjacent. Even if physically adjacent rows (and columns) are logically adjacent, there are other issues that preclude the possibility of identical physical and logical addresses. State-of-the-art memory ch... View full abstract»

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  • Modeling the reliability of a class of fault-tolerant VLSI/WSI systems based on multiple-level redundancy

    Publication Year: 1994, Page(s):737 - 748
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    A class of fault-tolerant Very Large Scale Integration (VLSI) and Wafer Scale Integration (WSI) schemes, called the multiple-level redundancy, which incorporates both hierarchical and element level redundancy has been proposed for the design of high yield and high reliability large area array processors. The residual redundancy left unused after successfully reconfiguring and eliminating the manuf... View full abstract»

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  • A fast method to evaluate the optimum number of spares in defect-tolerant integrated circuits

    Publication Year: 1994, Page(s):687 - 697
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (948 KB)

    We present a method to accelerate the search for the number of spares to be included in defect tolerant integrated circuits. Our method is obtained by bringing two modifications to a conventional evaluation method. The main motivations behind the development of this method are: the possibilities offered by the implementation of defect tolerance, the existence of many yield models, which may predic... View full abstract»

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  • Least upper bounds on OBDD sizes

    Publication Year: 1994, Page(s):764 - 767
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    This paper derives exact equations for the maximum number of nonterminal vertexes in reduced and quasi-reduced ordered binary decision diagrams (OBDD's). A reduced OBDD is reduced by both merging and deleting vertices, and a quasi-reduced OBDD is reduced only by merging. These formulas are used to tighten Lee's original bounds, and to correct the bounds recently reported by H.T. Liaw and C.S. Lin ... View full abstract»

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  • Design of CAECC - cellular automata based error correcting code

    Publication Year: 1994, Page(s):759 - 764
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    A new scheme for designing error detecting and error correcting codes around cellular automata (CA) is reported. A simple and efficient scheme for generating SEC-DED codes is presented which can also be extended for generating codes with higher distances. A CA-based hardware scheme for very fast decoding (and correcting) of the codewords is also reported View full abstract»

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  • Constant time sorting on reconfigurable meshes

    Publication Year: 1994, Page(s):749 - 751
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    We present a constant time sorting algorithm by adopting a 3D reconfigurable mesh with only O(n3/2) processors. Our algorithm is developed on an n1/2×n1/2×n1/2 3-D reconfigurable mesh. Moreover, we further extend the result to k-dimensional reconfigurable meshes for k⩾3. Consequently, an O(4 k+1) time sorting algorithm is obtai... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org