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IEEE Design & Test

Issue 3 • June 2015

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  • Front Cover

    Publication Year: 2015, Page(s): C1
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  • Cover 2

    Publication Year: 2015, Page(s): C2
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  • Masthead

    Publication Year: 2015, Page(s): 1
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  • Table of Contents

    Publication Year: 2015, Page(s): 2
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  • Departments [Table of Contents]

    Publication Year: 2015, Page(s): 3
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  • A Look at Asynchronous Design and Photonic Network-on-a-Chip (PNoC)

    Publication Year: 2015, Page(s): 4
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  • Asynchronous Design—Part 1: Overview and Recent Advances

    Publication Year: 2015, Page(s):5 - 18
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (908 KB) | HTML iconHTML

    An asynchronous design paradigm is capable of addressing the impact of increased process variability, power and thermal bottlenecks, high fault rates, aging, and scalability issues prevalent in emerging densely packed integrated circuits. The first part of the two-part article on asynchronous design presents a chronicle of past and recent commercial advances, as well as technical foundations, and ... View full abstract»

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  • Asynchronous Design—Part 2: Systems and Methodologies

    Publication Year: 2015, Page(s):19 - 28
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    This two-part article aims to provide both a short historical and technical overview of asynchronous design, as well as a snapshot of the state of the art. Part 1 covered foundations of asynchronous design, and highlighted recent applications, including commercial advances and use in emerging application areas. Part 2 focuses on methodologies for designing asynchronous systems, including basics of... View full abstract»

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  • Crosstalk Mitigation for High-Radix and Low-Diameter Photonic NoC Architectures

    Publication Year: 2015, Page(s):29 - 39
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1189 KB) | HTML iconHTML

    Photonic Network-on-chip (PNoC) is a promising alternative to design low-power and high-bandwidth interconnection infrastructure for multicore chips. The micro ring resonators, which are essential building blocks for designing PNoCs are susceptible to crosstalk that can notably degrade signal-to-noise ratio (SNR), reducing reliability of PNoCs. This paper proposes two novel encoding mechanisms to ... View full abstract»

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  • Educational Activities

    Publication Year: 2015, Page(s): 40
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  • IEEE D&T Roundtable to Cover ITC 2014 Panel on “Open Problems in Design, Verification, and Test: Why Is It (Not) Business as Usual?”

    Publication Year: 2015, Page(s):41 - 47
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  • Open Access Publishing

    Publication Year: 2015, Page(s): 48
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  • Test Technology TC Newsletter

    Publication Year: 2015, Page(s):49 - 50
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  • Phaser Data

    Publication Year: 2015, Page(s): 51
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  • CEDA Currents

    Publication Year: 2015, Page(s):52 - 53
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  • IEEE Proceedings

    Publication Year: 2015, Page(s): 54
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  • IEEE Was Here

    Publication Year: 2015, Page(s): 55
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  • Time Out of Mind

    Publication Year: 2015, Page(s): 56
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB) | HTML iconHTML

    Asynchronous designs, described in the two-part tutorial in this issue of IEEE Design & Test, is a methodology which has never caught on as well as it should. But I think it is going to, and in an unexpected way. Asynchronous methods for neuromorphic computing are mentioned briefly in the tutorial. Modeling the brain, an initiative already begun, is going to become very important. There are major ... View full abstract»

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  • Cover 3

    Publication Year: 2015, Page(s): C3
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  • Cover 4

    Publication Year: 2015, Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

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Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)