# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 24 of 24

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2015, Page(s): C2
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• ### Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors

Publication Year: 2015, Page(s):993 - 1004
Cited by:  Papers (1)
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An RLC model for on-chip power distribution networks (PDN) is presented for array and wire-bonded integrated circuits including interblock decoupling capacitors and C4 impedances. From the model, the supply noise produced by switching blocks as well as the impedance to ac ground as seen from any point of the circuit are calculated as a function of frequency and PDN parameters. The proposed method ... View full abstract»

• ### MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications

Publication Year: 2015, Page(s):1005 - 1016
Cited by:  Papers (9)
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For data-intensive applications, energy expended in on-chip computation constitutes only a small fraction of the total energy consumption. The primary contribution comes from transporting data between off-chip memory and on-chip computing elements-a limitation referred to as the Von-Neumann bottleneck. In such a scenario, improving the compute energy through parallel processing or on-chip hardware... View full abstract»

• ### Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management

Publication Year: 2015, Page(s):1017 - 1030
Cited by:  Papers (2)
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Dynamic thermal management (DTM) is commonly used to ensure reliable and safe operation in modern computing systems. DTM techniques are based on slowing down or shutting down parts of a system; hence, they effectively reduce system performance and thereby adversely impact applications. In this paper, we focus on real-time applications in which degradation in performance translates to a loss in app... View full abstract»

• ### Modeling and Detection of Hotspot in Shaded Photovoltaic Cells

Publication Year: 2015, Page(s):1031 - 1039
Cited by:  Papers (7)
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In this paper, we address the problem of modeling the thermal behavior of photovoltaic (PV) cells undergoing a hotspot condition. In case of shading, PV cells may experience a dramatic temperature increase, with consequent reduction of the provided power. Our model has been validated against experimental data, and has highlighted a counterintuitive PV cell behavior, that should be considered to im... View full abstract»

• ### Eleven Ways to Boost Your Synchronizer

Publication Year: 2015, Page(s):1040 - 1049
Cited by:  Papers (2)
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Synchronizers play an essential role in multiple clock domain systems-on-chip. The most common synchronizer consists of a series of pipelined flip-flops. Several factors influence the performance of synchronizers: circuit design, process technology, and operating conditions. Global factors apply to the entire integrated circuit, while others can be adjusted for each individual synchronizer in the ... View full abstract»

• ### Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures

Publication Year: 2015, Page(s):1050 - 1062
Cited by:  Papers (2)
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This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test schedu... View full abstract»

• ### Low-Power Programmable PRPG With Test Compression Capabilities

Publication Year: 2015, Page(s):1063 - 1076
Cited by:  Papers (3)
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This paper describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropria... View full abstract»

• ### Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs

Publication Year: 2015, Page(s):1077 - 1088
Cited by:  Papers (4)
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With the significant increase in the number of processing elements in NoC-based MPSoCs, communication becomes, increasingly, a critical resource for performance gains and quality-of-service (QoS) guarantees. The main gap observed in the NoC-based MPSoCs literature is the runtime adaptive techniques to meet QoS. In the absence of such techniques, the system user must statically define, for example,... View full abstract»

• ### An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi- $\mathrm{V}_{\rm DD}$ CMOS/SIMOX Techniques

Publication Year: 2015, Page(s):1089 - 1102
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Many of the current wireline networks are digitalized. In Japan, a synchronous digital hierarchy (SDH) system is installed in the public switched telephone network, and application data are transferred with a synchronous transfer module (STM). This paper presents an STM-16 frame termination VLSI fabricated with a 0.3-μm quintuple-metal CMOS/SIMOX process. To reduce power consumption, we emp... View full abstract»

• ### Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC

Publication Year: 2015, Page(s):1103 - 1110
Cited by:  Papers (3)
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A successive approximation register (SAR) analogto-digital converter (ADC) with a fixed antialiasing frequency that allows tradeoffs between power consumption and signal bandwidth is presented. The ADC, without increasing hardware complexity, can reduce power consumption significantly by skipping MSB conversions when they are unnecessary. By sampling and converting only the difference between two ... View full abstract»

• ### A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique

Publication Year: 2015, Page(s):1111 - 1122
Cited by:  Papers (16)
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This paper presents a design methodology for an ultra-low-power (ULP) and ultra-low-voltage (ULV) ultra-wideband (UWB) resistive-shunt feedback low-noise amplifier (LNA). The ULV circuit design challenges are discussed and a new biasing metric for ULV and ULP designs in deep-submicrometer CMOS technologies is introduced. Series inductive peaking in the feedback loop is analyzed and employed to enh... View full abstract»

• ### High-Frequency CMOS Active Inductor: Design Methodology and Noise Analysis

Publication Year: 2015, Page(s):1123 - 1136
Cited by:  Papers (4)
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The potential of active inductors (AIs) has been often reduced by lack of accurate design methodologies and limitations due to the inherent noise sources. This paper deals with these two open issues for a high-frequency CMOS AI characterized by high-quality factor, low-power consumption, and low noise. First, it reports an effective design methodology for the implementation of high-frequency CMOS ... View full abstract»

• ### Frequency-Tuning Negative-Conductance Boosted Structure and Applications for Low-Voltage Low-Power Wide-Tuning-Range VCO

Publication Year: 2015, Page(s):1137 - 1144
Cited by:  Papers (7)
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A frequency-tuning negative-conductance (-Gm) boosted structure and applications for a voltage-controlled oscillator (VCO) is presented in this paper. Analog tuning varactors connected to a -Gm boosted structure is proposed to significantly alleviate the limitation of the tuning range for the -Gm boosted structure, resulting in a low-voltage low-power wide-tuning-r... View full abstract»

• ### A CMOS PWM Transceiver Using Self-Referenced Edge Detection

Publication Year: 2015, Page(s):1145 - 1149
Cited by:  Papers (2)
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A CMOS pulsewidth modulation (PWM) transceiver circuit that exploits the self-referenced edge detection technique is presented. By comparing the rising edge that is self-delayed by about 0.5 T and the modulated falling edge in one carrier clock cycle, area-efficient and high-robustness (against timing fluctuations) edge detection enabling PWM communication is achieved without requiring elaborate p... View full abstract»

• ### An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation

Publication Year: 2015, Page(s):1150 - 1154
Cited by:  Papers (1)
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This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially reduces the number of multiplications per input sample and additions per input sample by 83% in comparison with individual implementation of each stan... View full abstract»

• ### A Fast Transient Response Flying-Capacitor Buck-Boost Converter Utilizing Pseudocurrent Dynamic Acceleration Techniques

Publication Year: 2015, Page(s):1155 - 1159
Cited by:  Papers (1)
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A fast transient response flying-capacitor buck-boost converter is proposed to improve the efficiency of conventional switched-capacitor converters. The voltage boost ratio of the proposed converter is 2D, where D is the duty cycle of the switching signal waveform. Furthermore, the proposed structure utilizes pseudocurrent dynamic acceleration techniques to achieve fast transient response when loa... View full abstract»

• ### On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ

Publication Year: 2015, Page(s):1160 - 1164
Cited by:  Papers (3)
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In this brief, three nonvolatile flip-flop (FF)/SRAM cells that utilize a single magnetic tunneling junction (MTJ) as nonvolatile resistive element are proposed. These cells have the same core (i.e., 6T) but they employ different numbers of MOSFETs to implement the so-called instantly ON, normally OFF mode of operation. The additional transistors are utilized for the restore operation to ensure th... View full abstract»

• ### True-Damage-Aware Enumerative Coding for Improving nand Flash Memory Endurance

Publication Year: 2015, Page(s):1165 - 1169
Cited by:  Papers (2)
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This brief presents a technique that can fully exploit the data dependency of flash memory cell damage to improve the program/erase (P/E) cycling endurance of nand flash memory. The key is to opportunistically leverage data lossless compressibility and utilize the compression gain to realize memory-damage-aware data manipulation to reduce the cycling-induced physical damage. Based upon experiments... View full abstract»

Publication Year: 2015, Page(s):1170 - 1174
Cited by:  Papers (10)
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Spin-torque transfer RAM (STT-RAM), a promising alternative to static RAM (SRAM) for reducing leakage power consumption, has been widely studied to mitigate the impact of its asymmetrically long write latency. However, physical effects of technology scaling down to 45 nm and below, in particular, process variation, introduce the previously unreported and alarming trends in read performance and rel... View full abstract»

• ### Demystifying Iddq Data With Process Variation for Automatic Chip Classification

Publication Year: 2015, Page(s):1175 - 1179
Cited by:  Papers (1)
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Iddq testing is an integral component of test suites for the screening of unreliable devices. As the scale of silicon technology continues shrinking, Iddq values and associated fluctuations increase. In addition, increased design complexity makes defect-induced leakage currents difficult to differentiate from full-chip currents. Consequently, traditional Iddq methods result in more test escapes an... View full abstract»

• ### Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications

Publication Year: 2015, Page(s):1180 - 1184
Cited by:  Papers (11)
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The need to support various digital signal processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Hence, improving the energy efficiency of multiplications is critical. In this brief, we propose multipl... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2015, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu