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# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 30

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2015, Page(s): C2
| PDF (129 KB)
• ### Guest Editorial Special Section on the 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014)

Publication Year: 2015, Page(s):1217 - 1219
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• ### Energy Efficient Group-Sort QRD Processor With On-Line Update for MIMO Channel Pre-Processing

Publication Year: 2015, Page(s):1220 - 1229
Cited by:  Papers (4)
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This paper presents a Sorted QR-Decomposition (SQRD) processor for 3GPP LTE-A system. It achieves energy-efficiency by co-optimizing techniques, such as heterogeneous processing, reconfigurable architecture, and dual-supply voltage operation. At algorithm level, a low-complexity hybrid decomposition scheme is adopted, which switches, depending on the energy distribution of spatial channels, betwee... View full abstract»

• ### On the Foundations of Stability Analysis of Power Systems in Time Scales

Publication Year: 2015, Page(s):1230 - 1239
Cited by:  Papers (2)
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Exploring singular perturbation and stability region theory, the foundations for decomposing the stability analysis of power systems in time scales is developed and a general algorithm, for stability analysis of power systems, which has transient stability analysis and quasi-steady state analysis as particular cases, is proposed. This algorithm bridges the gap between short and mid-term stability ... View full abstract»

• ### Estimation of Non-Idealities in Sigma-Delta Modulators for Test and Correction Using Unscented Kalman Filters

Publication Year: 2015, Page(s):1240 - 1249
Cited by:  Papers (2)
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In this paper, an enhanced unscented Kalman filter is used for the estimation of non-idealities in sigma-delta modulators. As sigma-delta modulator based analog-to-digital converters are known to be prone to performance degradation from many circuit non-idealities, testing and selection of the manufactured chips as well as post-correction procedures are required to ensure a reliable performance. I... View full abstract»

• ### A Phase-Interpolation and Quadrature-Generation Method Using Parametric Energy Transfer in CMOS

Publication Year: 2015, Page(s):1250 - 1259
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This work focuses on generation of quadrature clocks with high phase accuracy and low noise, while reducing area and power consumption. The design objective is to make these quadrature oscillators suitable for applications in power- and area-constrained SOCs. We demonstrate in this work quadrature clock generation using parametric capacitance modulation in CMOS technology. We present a quadrature-... View full abstract»

• ### Synchronization in On-Off Stochastic Networks: Windows of Opportunity

Publication Year: 2015, Page(s):1260 - 1269
Cited by:  Papers (11)
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We study dynamical networks whose topology and intrinsic parameters stochastically change, on a time scale that ranges from fast to slow. When switching is fast, the stochastic network synchronizes as long as synchronization in the averaged network, obtained by replacing the random variables by their mean, becomes stable. We apply a recently developed general theory of blinking systems to prove gl... View full abstract»

• ### A CMOS Current-Mode Magnetic Hall Sensor With Integrated Front-End

Publication Year: 2015, Page(s):1270 - 1278
Cited by:  Papers (20)
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A Hall magnetic sensor working in the current domain and its electronic interface are presented. The paper describes the physical sensor design and implementation in a standard CMOS technology, the transistor level design of its high sensitive front-end together with the sensor experimental characterization. The current-mode Hall sensor and the analog readout circuit have been fabricated using a 0... View full abstract»

• ### Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters

Publication Year: 2015, Page(s):1279 - 1287
Cited by:  Papers (7)
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Deterministic tree search algorithms for the design of multiplierless linear phase finite impulse response filters are generally time consuming. Many researches therefore focus on how to restrict the number of discrete values assigned to each coefficient during a tree search. In this paper, a two-step tree search algorithm is proposed. In the first step, a polynomial-time tree search algorithm whe... View full abstract»

• ### A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS

Publication Year: 2015, Page(s):1288 - 1295
Cited by:  Papers (2)
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A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce t... View full abstract»

• ### A Low-Power Architecture for Punctured Compressed Sensing and Estimation in Wireless Sensor-Nodes

Publication Year: 2015, Page(s):1296 - 1305
Cited by:  Papers (8)
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In wireless sensor nodes with a tight power budget, minimizing both the amount of transmitted data and the complexity of the algorithms used for data compression are fundamental in achieving long battery life-time. Compressed Sensing (CS) has been proposed to process incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. We show that the architecture i... View full abstract»

• ### Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters

Publication Year: 2015, Page(s):1306 - 1314
Cited by:  Papers (5)
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A dynamic path-mismatch calibration operating on direct derivative information (DDI) augments the reference-path equalization technique of that treats static mismatch errors in time-interleaved (TI) analog-to-digital converters (ADC). The approach results in a comprehensive background calibration of interleaved ADC arrays suitable for digitizing wideband inputs. The DDI of the analog input is prod... View full abstract»

• ### A Digital-Based Virtual Voltage Reference

Publication Year: 2015, Page(s):1315 - 1324
Cited by:  Papers (4)
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A novel virtual reference concept is introduced in this paper to design accurate, mostly digital, software-defined, process-supply-and-temperature (PVT)-independent voltage references suitable to replace conventional analog reference circuits in present day, low voltage, aggressively scaled, mainly digital integrated systems. The operation and the performance of references based on the proposed ap... View full abstract»

• ### Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit $\Delta\Sigma$ Modulators

Publication Year: 2015, Page(s):1325 - 1334
Cited by:  Papers (7)
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This paper presents a novel dynamic element matching (DEM) technique for multi-bit ΔΣ digital-to-analog converters (DACs). The proposed technique can address errors due to both static element mismatch and dynamic inter-symbol-interference (ISI). The proposed technique ensures no ISI-induced distortion even at large signal amplitudes by de-correlating the instantaneous number of DAC t... View full abstract»

• ### An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects

Publication Year: 2015, Page(s):1335 - 1344
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This paper presents an approximate closed-form transfer function model for diverse differential interconnects. The proposed model is simple, intuitive, and can accurately describe various interconnects satisfying the validity conditions which theoretically bound the approximation error. The proposed model also provides a conceptual circuit representation by analogy with an equivalent circuit model... View full abstract»

• ### Analysis of Current Efficiency for CMOS Class-B $LC$ Oscillators

Publication Year: 2015, Page(s):1345 - 1352
Cited by:  Papers (4)
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This paper focuses on the study of current efficiency in CMOS class-B LC oscillators. Exact expressions for current efficiency have been derived for the class-B oscillator. Theoretically, to achieve optimal figure-of-merit (FoM), the current efficiency in class-B oscillators is between 0.60 and 0.85, which revises the common assumption that current efficiency in all class-B oscillators is equal to... View full abstract»

• ### Variable Latency Speculative Han-Carlson Adder

Publication Year: 2015, Page(s):1353 - 1361
Cited by:  Papers (6)
| | PDF (2021 KB) | HTML

Variable latency adders have been recently proposed in literature. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time, but not always. The approximated adder is augmented with an error detection network that asserts an error signal when speculation fails. Speculative variable ... View full abstract»

• ### Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM

Publication Year: 2015, Page(s):1362 - 1371
Cited by:  Papers (3)
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Three-dimensional (3D) integration is promising to provide dramatic performance and energy efficiency improvement to 3D logic-DRAM integrated computing system, but also poses significant challenge to the yield. To address this challenge, this paper explores a way to leverage logic-DRAM co-design to reactivate unused spares and thereby enable the cost-efficient technique to repair 3D integration-in... View full abstract»

• ### A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation

Publication Year: 2015, Page(s):1372 - 1381
Cited by:  Papers (5)
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A domain specific multicore processor for public-key cryptography is proposed in this paper. This processor provides flexible and efficient computation for various forms of RSA and ECC algorithms, fulfilling low-latency or high-throughput requirements of different application scenarios. By using a heterogeneous multicore architecture, the proposed processor enables high speed parallel implementati... View full abstract»

• ### Mixing Drivers in Clock-Tree for Power Supply Noise Reduction

Publication Year: 2015, Page(s):1382 - 1391
Cited by:  Papers (2)
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In today's process technologies, power supply noise may cause serious clock jitter and circuit malfunction. Noise occurs by the fast and simultaneous voltage switching. A primary contributor to the noise is the clock-tree and the underlying sequential circuits that switch simultaneously, thus causing high current peaks. This work proposes to spread the switching of the clock-tree drivers, while ma... View full abstract»

• ### A Memristor-Based Continuous-Time Digital FIR Filter for Biomedical Signal Processing

Publication Year: 2015, Page(s):1392 - 1401
Cited by:  Papers (4)
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This paper proposes a new timing storage circuit based on memristors. Its ability to store and reproduce timing information in an analog manner without performing quantization can be useful for a wide range of applications. For continuous-time (CT) digital filters, the power and area costly analog delay blocks, which are usually implemented as inverter chains or their variants, can be replaced by ... View full abstract»

• ### A Novel Design for Memristor-Based Logic Switch and Crossbar Circuits

Publication Year: 2015, Page(s):1402 - 1411
Cited by:  Papers (18)
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Recently, it has been demonstrated that memristors can be utilized as logic gates, control switches as well as memory elements. In this paper, we analyze the different AND, OR, and NOT logic gates which are based on memristors. In addition, a novel design for a memristor-based switch is presented, which can be used in the peripheral read/write circuits of the memristor-based memory. Moreover, meth... View full abstract»

• ### A Comparative Analysis of Adaptive Digital Predistortion Algorithms for Multiple Antenna Transmitters

Publication Year: 2015, Page(s):1412 - 1420
Cited by:  Papers (7)
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This paper presents a comparative study of adaptive algorithms for digital predistortion (DPD) in multiple antenna transmitters. Crossover predistorter (CO-DPD) and crosstalk canceling predistorter (CTC-DPD) were proposed to overcome the deleterious effect of RF crosstalk before the power amplifiers (PA) on digital predistortion (DPD) in multiple antenna transmitters. This paper discusses the line... View full abstract»

• ### High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

Publication Year: 2015, Page(s):1421 - 1430
Cited by:  Papers (6)
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This paper presents architecture of block-level-parallel layered decoder for irregular LDPC code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11n (WiFi) wireless-communication standard. We have proposed efficient comparison techniques for both column and row layered schedule and rejection-based high-speed circuits to compute the two minimum values from multip... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK