By Topic

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 2 • Date June 1994

Filter Results

Displaying Results 1 - 13 of 13
  • On area/depth trade-off in LUT-based FPGA technology mapping

    Page(s): 137 - 148
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1244 KB)  

    In this paper, we study the area and depth trade-off in lookup-table (LUT) based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a sequence of depth relaxation operations and area-minimizing mapping procedures to produce a set of mapping solutions for a given design with smooth area and depth trade-off. As the core of the area minimization step, we have developed a polynomial time optimal algorithm for computing an area-minimum mapping solution without node duplication for a K-bounded general Boolean network, which makes a significant step towards complete understanding of the general area minimization problem in FPGA technology mapping. The experimental results on MCNC benchmark circuits show that our solution sets outperform the solutions produced by most existing mapping algorithms in terms of both area and depth minimization.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations

    Page(s): 149 - 156
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (939 KB)  

    We present the design and implementation of a bus-monitor unit targeted for the design of highly reliable fault-tolerant systems. The bus-monitor is designed using differential cascode voltage switch (DCVS) logic, whose inherent characteristics result in self-checking circuits. It is implemented in an application specific integrated circuit that can be used to implement a variety of fault-tolerant architectures including triple modular redundant and hybrid configurations. The unit is capable of detecting and correcting failures in the redundant modules by monitoring their respective buses, and it delivers fault-free data to the destination modules. The unit is also capable of detecting faults occurring in the unit itself by utilizing the fault secure properties of DCVS logic. In this paper, we present the operation of the bus-monitor unit and we describe its DCVS design and implementation, as well as the performance characteristics of the prototype chips. Finally, we illustrate how the bus-monitor unit(s) can be used to implement highly reliable fault-tolerant architectures, and we demonstrate that architectures designed using the developed unit(s) exhibit higher reliability compared to the ones implemented with CMOS logic, using the same number of computational resources.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • ALADIN: a multilevel testability analyzer for VLSI system design

    Page(s): 157 - 171
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1733 KB)  

    In order to cope with tomorrow's challenges in the microelectronic market, the reliability of the first phases of the design process must be improved. The possibility of applying techniques for testability analysis at these abstract design levels can considerably help in achieving this goal, reducing at the same time system design costs. In this paper we introduce a novel approach for the application of functional testability at system design level and demonstrate the possibility of its application in an industrial environment. Testability conditions referring to both regular and irregular topologies have been defined, formalized and inserted into the knowledge base of the expert system, ALADIN. This tool operates as a testability analyzer able to identify critical areas for testability in designs whose functional modules and local interconnections are known and described in standard VHDL. The architecture of the tool has been defined in order to satisfy the users' requirements including the integrability into a standard CAD design flow through standard I/O interfaces. Then its application to both a regular and an irregular topology are presented in order to show on real examples which testability conditions apply, and how the tool operates in order to reach the testability assessment. From these industrial case studies, figures of merit are derived from which it is possible to evaluate the importance of the application of such a methodology to system level design.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Clairvoyant: a synthesis system for production-based specification

    Page(s): 172 - 185
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1595 KB)  

    This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the specification of the control aspects and data-flow aspects of the design. The control is implicitly described via the production hierarchy, while the data-flow is described as action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a controlling machine from the PBS and this process is not impacted by the possibly exponentially larger deterministic state space of the designs. The encodings generated by the constructions compare favorably to encodings derived using graph-based state encoding techniques in terms of logic complexity and logic depth. These construction techniques utilize recent advances in BDD techniques.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • RSYN: a system for automated synthesis of reliable multilevel circuits

    Page(s): 186 - 195
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1084 KB)  

    Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A syntax-directed translation for the synthesis of delay-insensitive circuits

    Page(s): 196 - 210
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1675 KB)  

    A syntax-directed translation procedure for the synthesis of delay-insensitive circuits from graph-theoretic specifications is presented. No isochronic fork assumption is required for the correct operation of the synthesized circuits. The synthesized circuits are different from those obtained from Ebergen's synthesis method. In Ebergen's circuits, the voltage levels of a set of wires are used to encode which input events are most recently received. Special circuit elements (the N-element or the RCEL element) and two-phase to four-phase converters are needed to change the voltage levels of the encoding wires when input events are received. In the circuits obtained from the method in this paper, the wires encoding which input events are most recently received are the outputs of the toggles. When input events are received, they are sent directly or via demultiplexers to the toggles to change the voltage levels at their outputs. Two-phase to four-phase converters are not needed. The synthesis method is compared with Ebergen's synthesis method.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimal and heuristic algorithms for solving the binding problem

    Page(s): 211 - 225
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1525 KB)  

    In this paper we present an optimal and a heuristic approach to solve the binding problem which occurs in high-level synthesis of digital systems. The optimal approach is based on an integer linear programming formulation. Given that such an approach is not practical for large problems, we then derive a heuristic from the ILP formulation which produces very good solutions in order of seconds. The heuristic is based on a network flow model and also considers floorplanning during the design process to minimize the interconnection area.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Partial address directory for cache access

    Page(s): 226 - 240
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1578 KB)  

    In most high performance computers the speeds of cache accessing are critical in determining the cycle times. A classical method for designing set-associative caches is to late-select array data based on the results of cache directory lookups. The impact on the critical path timing due to late-select will become more significant in future microprocessors with very high clock frequencies. In this paper we propose a new approach to the optimization of array access timing for set-associative caches. The basic idea is to utilize a relatively small partial address directory (PAD) for fast and accurate approximations of cache access coordinates. The PAD can speed up most cache array access by accurately predicting cache locations without having to wait for results from conventional cache directory lookups. Occasionally when the PAD guesses wrong, a memory access can be re-issued with only 1-cycle delays. The PAD may be closely integrated with the array design. The effectiveness of the PAD method is analyzed through combinatorial and simulation studies.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • BiCMOS logic testing

    Page(s): 241 - 248
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (754 KB)  

    With the anticipated growth of BiCMOS technology for high-performance ASIC design, the issue of testing takes on great significance. This paper addresses the testing of BiCMOS logic circuits. Since many different implementations of BiCMOS gates have been proposed, four representative ones are studied. The adequacy of stuck-at, quiescent current, and delay testing are examined based on circuit level faults. It is demonstrated that a large portion of the defects cannot be detected by common stuck-at or quiescent current tests since they manifest themselves as delay faults. By using the results presented, the test methodologies and the logic families can be ranked based on fault coverage. This ranking can then be used to help decide which BiCMOS solution is proper for a given application.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A statistical study of defect maps of large area VLSI IC's

    Page(s): 249 - 256
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (790 KB)  

    Defect maps of 57 wafers containing large area VLSI IC's were analyzed in order to find a good match between the empirical distribution of defects and a theoretical model. Our main result is that the commonly employed models, most notably, the large area clustering negative binomial distribution, do not provide a sufficiently good match for these large area IC's. Only the recently proposed medium size clustering model is close enough to the empirical distribution. An even better match can be obtained either by combining two theoretical distributions or by a "censoring" procedure in which the worst chips are ignored. Another goal of the study was to find out whether certain portions of either the chip or the wafer had more defects than the others.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On concurrent error location and correction of FFT networks

    Page(s): 257 - 260
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (415 KB)  

    Fault tolerance has been one of the major issues for the VLSI based FFT networks. In this paper, two efficient approaches for concurrent error location and correction of FFT networks are proposed. Using our approach, a faulty component can be located at an additional try followed by log/sub 2/m comparisons of m corrupted outputs. An error can also be corrected, once it is detected, at a small modification of basic module with an additional try. Moreover, our approaches are general in the sense that they can be implemented with any concurrent error detection scheme employing a checksum approach for FFT networks.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low power design using double edge triggered flip-flops

    Page(s): 261 - 265
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (570 KB)  

    In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The analysis includes an implementation independent study on the effect of input sequences in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algorithms and bounds for layer assignment of MCM routing

    Page(s): 265 - 270
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (595 KB)  

    We present new algorithms for the layer assignment problem of multichip modules (MCM's). Our algorithms produce results that require between 70% and 25% of the number of layers required by the previous algorithms. We also present a new model for the problem that results in a better utilization of the routing area of the MCM, thus reducing the number of required layers even more. We provide lower and upper bounds on the performance of our algorithms which are tighter than the ones obtained before. Through our experimental results we show that the solutions obtained by our algorithms are close to the lower bounds.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Yehea Ismail
CND Director
American University of Cairo and Zewail City of Science and Technology
New Cairo, Egypt
y.ismail@aucegypt.edu