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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 2 • June 1994

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Displaying Results 1 - 13 of 13
  • On area/depth trade-off in LUT-based FPGA technology mapping

    Publication Year: 1994, Page(s):137 - 148
    Cited by:  Papers (50)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1244 KB)

    In this paper, we study the area and depth trade-off in lookup-table (LUT) based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a sequence of depth relaxation operations and area-minimizing mapping procedures to produce a set of mapping solutions for a given design with smooth area and depth trade-off. As the core of the area minimization step, we have develope... View full abstract»

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  • Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations

    Publication Year: 1994, Page(s):149 - 156
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (939 KB)

    We present the design and implementation of a bus-monitor unit targeted for the design of highly reliable fault-tolerant systems. The bus-monitor is designed using differential cascode voltage switch (DCVS) logic, whose inherent characteristics result in self-checking circuits. It is implemented in an application specific integrated circuit that can be used to implement a variety of fault-tolerant... View full abstract»

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  • ALADIN: a multilevel testability analyzer for VLSI system design

    Publication Year: 1994, Page(s):157 - 171
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1733 KB)

    In order to cope with tomorrow's challenges in the microelectronic market, the reliability of the first phases of the design process must be improved. The possibility of applying techniques for testability analysis at these abstract design levels can considerably help in achieving this goal, reducing at the same time system design costs. In this paper we introduce a novel approach for the applicat... View full abstract»

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  • Clairvoyant: a synthesis system for production-based specification

    Publication Year: 1994, Page(s):172 - 185
    Cited by:  Papers (42)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1595 KB)

    This paper describes a new high-level synthesis system based on the hierarchical production based specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables, and that the designer does not describe a particular form of implementation. The production-based specification also separates the sp... View full abstract»

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  • RSYN: a system for automated synthesis of reliable multilevel circuits

    Publication Year: 1994, Page(s):186 - 195
    Cited by:  Papers (76)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1084 KB)

    Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic s... View full abstract»

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  • A syntax-directed translation for the synthesis of delay-insensitive circuits

    Publication Year: 1994, Page(s):196 - 210
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1675 KB)

    A syntax-directed translation procedure for the synthesis of delay-insensitive circuits from graph-theoretic specifications is presented. No isochronic fork assumption is required for the correct operation of the synthesized circuits. The synthesized circuits are different from those obtained from Ebergen's synthesis method. In Ebergen's circuits, the voltage levels of a set of wires are used to e... View full abstract»

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  • Optimal and heuristic algorithms for solving the binding problem

    Publication Year: 1994, Page(s):211 - 225
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1525 KB)

    In this paper we present an optimal and a heuristic approach to solve the binding problem which occurs in high-level synthesis of digital systems. The optimal approach is based on an integer linear programming formulation. Given that such an approach is not practical for large problems, we then derive a heuristic from the ILP formulation which produces very good solutions in order of seconds. The ... View full abstract»

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  • Partial address directory for cache access

    Publication Year: 1994, Page(s):226 - 240
    Cited by:  Papers (9)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1578 KB)

    In most high performance computers the speeds of cache accessing are critical in determining the cycle times. A classical method for designing set-associative caches is to late-select array data based on the results of cache directory lookups. The impact on the critical path timing due to late-select will become more significant in future microprocessors with very high clock frequencies. In this p... View full abstract»

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  • BiCMOS logic testing

    Publication Year: 1994, Page(s):241 - 248
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (754 KB)

    With the anticipated growth of BiCMOS technology for high-performance ASIC design, the issue of testing takes on great significance. This paper addresses the testing of BiCMOS logic circuits. Since many different implementations of BiCMOS gates have been proposed, four representative ones are studied. The adequacy of stuck-at, quiescent current, and delay testing are examined based on circuit leve... View full abstract»

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  • A statistical study of defect maps of large area VLSI IC's

    Publication Year: 1994, Page(s):249 - 256
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (790 KB)

    Defect maps of 57 wafers containing large area VLSI IC's were analyzed in order to find a good match between the empirical distribution of defects and a theoretical model. Our main result is that the commonly employed models, most notably, the large area clustering negative binomial distribution, do not provide a sufficiently good match for these large area IC's. Only the recently proposed medium ... View full abstract»

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  • On concurrent error location and correction of FFT networks

    Publication Year: 1994, Page(s):257 - 260
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (415 KB)

    Fault tolerance has been one of the major issues for the VLSI based FFT networks. In this paper, two efficient approaches for concurrent error location and correction of FFT networks are proposed. Using our approach, a faulty component can be located at an additional try followed by log/sub 2/m comparisons of m corrupted outputs. An error can also be corrected, once it is detected, at a small modi... View full abstract»

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  • Low power design using double edge triggered flip-flops

    Publication Year: 1994, Page(s):261 - 265
    Cited by:  Papers (70)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (570 KB)

    In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compa... View full abstract»

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  • Algorithms and bounds for layer assignment of MCM routing

    Publication Year: 1994, Page(s):265 - 270
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (595 KB)

    We present new algorithms for the layer assignment problem of multichip modules (MCM's). Our algorithms produce results that require between 70% and 25% of the number of layers required by the previous algorithms. We also present a new model for the problem that results in a better utilization of the routing area of the MCM, thus reducing the number of required layers even more. We provide lower a... View full abstract»

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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu