# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 24 of 24

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2015, Page(s): C2
| PDF (136 KB)
• ### Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips

Publication Year: 2015, Page(s):217 - 221
Cited by:  Papers (1)
| | PDF (700 KB) | HTML

This brief presents a wide-range temperature sensor with process compensation and nonlinear calibration for HV chip thermal monitoring. Due to a high supply voltage and a large current, HV chips are prone to overheating; thus, they require on-chip temperature sensors to monitor thermal variation. The voltage difference between the drain and source voltages of a metal-oxide-semiconductor, i.e., V View full abstract»

• ### Characteristics of Single- and Multiple-Frequency Impedance Matching Networks

Publication Year: 2015, Page(s):222 - 225
Cited by:  Papers (1)
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The simplest network for matching a load resistance RL to a source resistance Rs at a single frequency is analyzed to find an expression for the matching bandwidth with a specified tolerance on the reflection coefficient. The results are used to find the characteristics of dual- and triple-frequency impedance matching networks, designed by applying frequency transformation to... View full abstract»

• ### Adaptive Background Estimation for Static Nonlinearity Mismatches in Two-Channel TIADCs

Publication Year: 2015, Page(s):226 - 230
Cited by:  Papers (4)
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Due to channel mismatches in time-interleaved analog-to-digital converters (TIADCs), estimation and compensation methods are required to restore the resolution of the individual converters. Whereas several methods exist for linear mismatches, nonlinearity mismatches have not been widely investigated. This brief presents an adaptive background estimation method for nonlinearity mismatches in two-ch... View full abstract»

• ### A MOS Parametric Integrator With Improved Linearity for SC $SigmaDelta$ Modulators

Publication Year: 2015, Page(s):231 - 235
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This brief presents a double complimentary metal- oxide-semiconductor (MOS) parametric integrator (DCMPI) with improved linearity characteristics for wideband switched-capacitor sigma-delta (ΣΔ) modulators. Compared with the MOS parametric integrator [1], the proposed circuit achieves similar power, noise, and speed performance, while its linearity characteristics and transfer functi... View full abstract»

• ### A Low-Voltage Sense Amplifier for Embedded Flash Memories

Publication Year: 2015, Page(s):236 - 240
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This brief presents a novel sense amplifier with an enhanced current sensing method for embedded flash memories, capable of operating at a voltage as low as 1.2 V. A dynamic bit-line clamping circuit and a novel reference voltage generation circuit are also employed to improve the precharge speed and sensing window under low power supply voltage. The sense amplifier was implemented in a flash real... View full abstract»

• ### A Multibit Delta–Sigma Modulator With Double Noise-Shaped Segmentation

Publication Year: 2015, Page(s):241 - 245
Cited by:  Papers (4)
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This brief proposes a low-power architecture for a discrete-time (DT) delta-sigma modulator to take full advantages of increased quantization levels. In the proposed architecture, noise-shaped segmentation is applied to both the quantizer and the feedback digital-to-analog converter to maintain a high resolution and a high linearity and, at the same time, keep the hardware complexity low. This lea... View full abstract»

• ### A 0.0045- $\hbox{mm}^{2}$ 32.4- $\mu\hbox{W}$ Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

Publication Year: 2015, Page(s):246 - 250
Cited by:  Papers (6)
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This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact micropower two-stage amplifier for wide capacitive load (CL) drivability. It features: 1) a valuable left half-plane zero to enhance the closed-loop stability over a wide range of CL; 2) no extra bias circuit and power, as the CM is embedded into the first... View full abstract»

• ### A New Two-Phase Stationary-Frame-Based Enhanced PLL for Three-Phase Grid Synchronization

Publication Year: 2015, Page(s):251 - 255
Cited by:  Papers (2)
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In this brief, a new two-phase stationary-frame-based enhanced phase-locked loop (TPSF-EPLL) is proposed for detecting the amplitude, phase angle, and frequency of a three-phase grid. The differential equations of the proposed TPSF-EPLL are originally derived based on minimizing the cost function with a gradient descent algorithm. Moreover, the system structure, the design guidelines of each param... View full abstract»

• ### Behavioral Analysis and Optimization of CMOS CML Dividers for Millimeter-Wave Applications

Publication Year: 2015, Page(s):256 - 260
Cited by:  Papers (1)
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Current-mode logic (CML) dividers are widely used in radio-frequency and millimeter-wave transceivers and frequency synthesizers for its wide division range. In this brief, a general analysis and optimization methodology of complimentary metal-oxide-semiconductor CML dividers based on the second-order approximation of transconductance is presented for the first time. Mechanisms of asymmetric sensi... View full abstract»

• ### Generalized Quadrature Data Weighted Averaging

Publication Year: 2015, Page(s):261 - 265
Cited by:  Papers (1)
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This brief focuses on quadrature multibit digital-to-analog conversion with data weighted averaging (DWA) as a linearization method. Previous study on generalized DWA is expanded here, into the complex domain, and is compared with prior art on complex DWA. It will be shown that the generalized DWA in the complex domain has several advantages such as reduced complexity, reduced spurious behavior, a... View full abstract»

• ### A Low-Power Architecture for the Design of a One-Dimensional Median Filter

Publication Year: 2015, Page(s):266 - 270
Cited by:  Papers (3)
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This brief presents a low-power architecture for the design of a one-dimension median filter. It is a word-level two-stage pipelined filter, receiving an input sample and generating a median output at each machine cycle. The power consumption is reduced by decreasing the number of signal transitions in the circuit. This can be done by keeping the stored samples immobile in the window through the u... View full abstract»

• ### An Improved NLMS Algorithm in Sparse Systems Against Noisy Input Signals

Publication Year: 2015, Page(s):271 - 275
Cited by:  Papers (4)
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This brief proposes a novel normalized least mean square algorithm that is characterized by robustness against noisy input signals. To compensate for the bias caused by the input noise that is added at the filter input, a derivation method based on reasonable assumptions finds a bias-compensating vector. Moreover, the proposed algorithm has a fast convergence rate when applied to sparse systems, o... View full abstract»

• ### Matrix-Interpolation-Based Parametric Model Order Reduction for Multiconductor Transmission Lines With Delays

Publication Year: 2015, Page(s):276 - 280
Cited by:  Papers (3)
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A novel parametric model order reduction technique based on matrix interpolation for multiconductor transmission lines (MTLs) with delays having design parameter variations is proposed in this brief. Matrix interpolation overcomes the oversize problem caused by input-output system-level interpolation-based parametric macromodels. The reduced state-space matrices are obtained using a higher-order K... View full abstract»

• ### Event-Based Consensus Control for a Linear Directed Multiagent System With Time Delay

Publication Year: 2015, Page(s):281 - 285
Cited by:  Papers (9)
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By utilizing the event-based control strategy, this brief deals with the consensus problem of a linear directed multiagent system with time delay. In order to avoid the continuous inter-agents communications and frequent controller updates, the control strategy is put forward with an event-triggered function consisting of the measurement error and a threshold based on the neighbors' discrete state... View full abstract»

• ### Optimization of EVM Through Diode Bias Control Using a Blind Algorithm Applied to Multiport Receivers

Publication Year: 2015, Page(s):286 - 290
Cited by:  Papers (1)
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In this brief, we developed a detailed Simulink model that emulates the radio frequency and digital base band of a six-port receiver. In contrast to other results published in the literature, we not only provide a controlled continuous bias to the diodes. We propose a novel algorithm that reduces the error vector magnitude (EVM) by adaptively controlling the diode bias point. We will also show tha... View full abstract»

• ### An Analysis of the Tradeoff Between the Energy and Spectrum Efficiencies in an Uplink Massive MIMO-OFDM System

Publication Year: 2015, Page(s):291 - 295
Cited by:  Papers (14)
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This brief mainly investigates energy efficiency (EE) and spectrum efficiency (SE) for the uplink massive multiple-input-multiple-output orthogonal frequency-division multiplexing system in a single-cell environment. An approximate SE expression is first derived by employing the maximum ratio combination or zero-forcing detection at the base station. Then, the theoretical tradeoff between EE and S... View full abstract»

• ### Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS

Publication Year: 2015, Page(s):296 - 300
Cited by:  Papers (2)
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A highly reconfigurable merged analog baseband (MABB) with not only tunable bandwidth (BW), gain, and order but also reconfigurable power, noise, and linearity is proposed for multistandard integrated wireless receivers in this brief. The MABB could arrange the total gain to different stages for noise and linearity tradeoffs by introducing the merged biquad topology. To save power, the operational... View full abstract»

• ### An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes

Publication Year: 2015, Page(s):301 - 305
Cited by:  Papers (1)
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This brief presents an area-efficient relaxed half-stochastic nonbinary low-density parity-check (NB-LDPC) decoder. A novel decoding algorithm, namely, cumulative tracking forecast memory with concealing channel values (CTFM-CC) is proposed to reduce algorithm complexity and maintain bit-error-rate performance as well. Furthermore, the hardware complexity of variable node units (VNUs) is reduced t... View full abstract»

• ### Partially Parallel Encoder Architecture for Long Polar Codes

Publication Year: 2015, Page(s):306 - 310
Cited by:  Papers (11)
| | PDF (652 KB) | HTML

Due to the channel achieving property, the polar code has become one of the most favorable error-correcting codes. As the polar code achieves the property asymptotically, however, it should be long enough to have a good error-correcting performance. Although the previous fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the huge hardware ... View full abstract»

• ### Selectively Sampled Subharmonic-Free Digital Current Mode Control Using Direct Duty Control

Publication Year: 2015, Page(s):311 - 315
Cited by:  Papers (2)
| | PDF (1045 KB) | HTML

Benefits of digital current mode control are often limited by the choice of a current-loop sampling rate. A higher rate requires a fast analog-to-digital converter that consumes substantial power and increases cost. A lower rate often results in subharmonic oscillations, even using a programmable ramp compensation. This brief proposes a simple technique to compute the steady-state duty ratio in re... View full abstract»

• ### IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2015, Page(s): 316
| PDF (108 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2015, Page(s): C3
| PDF (118 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org