IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Publication Year: 2015, Page(s):C1 - C4
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• IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2015, Page(s): C2
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• Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

Publication Year: 2015, Page(s):413 - 421
Cited by:  Papers (2)
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In this paper, we propose a level-converting retention flip-flop (RFF) for ZigBee systems-on-chips (SoCs). The proposed RFF allows the voltage regulator that generates the core supply voltage (VDD,core) to be turned off in the standby mode, and it thus reduces the standby power of the ZigBee SoCs. The logic states are retained in a slave latch composed of thick-oxide transistors using an I/O suppl... View full abstract»

• A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology

Publication Year: 2015, Page(s):422 - 434
Cited by:  Papers (6)
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A boosting pass gate (BPG) suitable for a programmable routing switch including a c-axis aligned crystal In-Ga-Zn-O (CAAC-IGZO) field effect transistor (FET) is proposed. The CAAC-IGZO is one of crystalline oxide semiconductors (OS). The proposed BPG (OS-based BPG, OS BPG) has a combination of a pass gate (PG) and a configuration memory (CM) cell utilizing a CAAC-IGZO FET with extremely low OFF-st... View full abstract»

• Low-Cost On-Chip Clock Jitter Measurement Scheme

Publication Year: 2015, Page(s):435 - 443
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In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolu... View full abstract»

• A Self-Powered High-Efficiency Rectifier With Automatic Resetting of Transducer Capacitance in Piezoelectric Energy Harvesting Systems

Publication Year: 2015, Page(s):444 - 453
Cited by:  Papers (8)
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This paper presents a self-powered rectifier for piezoelectric energy harvesting applications, and the key idea of the proposed system is to reset the transducer capacitor at optimal instants to maximize the extracted power. The proposed rectifier consists of two switches and two active diodes. The switches discharge the transducer capacitor at optimal instants two times for every cycle. The activ... View full abstract»

• Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications

Publication Year: 2015, Page(s):454 - 465
Cited by:  Papers (7)
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In this paper, we introduce a novel reconfigurable hardware architecture for computing the polynomial matrix multiplication (PMM) of polynomial matrices and/or polynomial vectors. The proposed algorithm exploits an extension of the fast convolution technique to multiple-input multiple-output systems. The proposed architecture is the first one devoted to the hardware implementation of PMM. Hardware... View full abstract»

• Diagnosis and Layout Aware (DLA) Scan Chain Stitching

Publication Year: 2015, Page(s):466 - 479
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Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, the chain diagnostic resolution may still be bad. In this paper, we propose a novel pattern-independent diagnosis and layout aware (DLA) scan chain stitching method: 1) the resolution is improved by increasing and properly distributing the sensitive scan cells, which can capture usef... View full abstract»

• A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits

Publication Year: 2015, Page(s):480 - 492
Cited by:  Papers (2)
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This paper presents a new parallel shooting-Newton method based on a graphic processing unit (GPU)-accelerated periodic Arnoldi shooting solver (GAPAS) for fast periodic steady-state analysis of radio frequency/millimeter-wave integrated circuits. The new algorithm first explores a periodic structure of the state matrix by using a periodic Arnoldi algorithm for computing the resulting structured K... View full abstract»

• Economizing TSV Resources in 3-D Network-on-Chip Design

Publication Year: 2015, Page(s):493 - 506
Cited by:  Papers (7)
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The confluence of 3-D integration and network-on-chip (NoC) provides an effective solution to the scalability problem of on-chip interconnects. In 3-D integration, through-silicon via (TSV) is considered to be the most promising bonding technology. However, TSVs are also precious link resources because they consume significant chip area and possibly lead to routing congestion in the physical desig... View full abstract»

• Demonstrating HW–SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane

Publication Year: 2015, Page(s):507 - 519
Cited by:  Papers (1)
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Transient errors are a major concern for the correct operation of low-level cache memories. Aggressive integration requires effective mitigation of such errors, without extreme overheads in power, timing, or silicon area. We demonstrate a hybrid (hardware-software) scheme that mitigates bit flips in data that reside in low-level caches. The methodology is shown to be applicable in streaming applic... View full abstract»

• Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache

Publication Year: 2015, Page(s):520 - 533
Cited by:  Papers (1)
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Nonvolatile memory such as magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with SRAM. 3-D integration technology using through-silicon vias enables stacking disparate memory technologies (e.g., SRAM and MRAM) together onto chip-multiprocessors (CMPs). The use of hybrid memories as an on-chip cache can take a... View full abstract»

• Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction

Publication Year: 2015, Page(s):534 - 543
Cited by:  Papers (6)
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We propose an efficient physics-based mixed-mode statistical simulation methodology for nanoscale devices and circuits. Here, 3-D Technology Computer Aided Design models pose a barrier for efficient simulation of variability as they generally involve millions of nodes in their mesh representations. The proposed methodology, which has been implemented for FinFET/tri-gate static random access memory... View full abstract»

• Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

Publication Year: 2015, Page(s):544 - 556
Cited by:  Papers (2)
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Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = -Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. ... View full abstract»

• A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS

Publication Year: 2015, Page(s):557 - 566
Cited by:  Papers (2)
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This paper presents a digital-subranging (sub-R) analog-to-digital conversion (ADC) architecture to improve the operation speed of sub-R ADCs. Long latency between coarse and fine conversions will slow down the conventional sub-R ADCs. The proposed digital-sub-R uses digital circuits to implement the sub-R function and shorten this latency, thus benefits the CMOS scaling. Furthermore, the dynamic ... View full abstract»

• Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line

Publication Year: 2015, Page(s):567 - 574
Cited by:  Papers (7)
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Previous high-performance delay-locked loops (DLLs) were designed in a full-custom design flow that is labor-intensive. Most of those DLLs require tens to hundreds of clock cycles to achieve synchronization of the clock signal. This paper presents an all-digital DLL (ADDLL) with constant acquisition cycles in a cell-based design flow. The proposed ADDLL circuit can acquire the phase of a clock sig... View full abstract»

• Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms

Publication Year: 2015, Page(s):575 - 579
Cited by:  Papers (3)
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In this brief, we propose an efficient parallel finite difference-based thermal simulation algorithm for 3-D-integrated circuits (ICs) using generalized minimum residual method (GMRES) solver on CPU-graphic processing unit (GPU) platforms. First, the new method starts from basic physics-based heat equations to model 3-D-ICs with intertier liquid cooling microchannels and directly solves the result... View full abstract»

• Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs

Publication Year: 2015, Page(s):580 - 583
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Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD... View full abstract»

• A Synergetic Use of Bloom Filters for Error Detection and Correction

Publication Year: 2015, Page(s):584 - 587
Cited by:  Papers (2)
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Bloom filters (BFs) provide a fast and efficient way to check whether a given element belongs to a set. The BFs are used in numerous applications, for example, in communications and networking. There is also ongoing research to extend and enhance BFs and to use them in new scenarios. Reliability is becoming a challenge for advanced electronic circuits as the number of errors due to manufacturing v... View full abstract»

• An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS

Publication Year: 2015, Page(s):588 - 592
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As the data rate has been increased over 10 Gb/s with copper interconnect, the intersymbol interference (ISI) caused from the channel loss should be compensated. While a decision feedback equalizer (DFE), which is widely used in the receiver can compensate the ISI, its ability to enhance the signal-to-noise ratio (SNR) is limited especially for high frequency data patterns (alternating data patter... View full abstract»

• Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set

Publication Year: 2015, Page(s):593 - 597
Cited by:  Papers (1)
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A low-power test generation procedure that was developed earlier merges broadside test cubes that are derived from functional broadside tests in order to generate a low-power broadside test set. This has several advantages, most importantly, that test cubes, which are derived from functional broadside tests, create functional operation conditions in subcircuits around the sites of detected faults.... View full abstract»

• A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS

Publication Year: 2015, Page(s):598 - 602
Cited by:  Papers (2)
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In this brief, we present a novel architecture for pseudorandom (PN) code acquisition based on statistical error compensation (SEC), which achieves significant power savings. SEC treats errors in hardware as noise in communication networks, and employs robust estimation theory to compensate for errors. We apply SEC to a 256-tap PN code acquisition filter in a 180-nm CMOS process. Multiple (five) d... View full abstract»

• Arithmetic-Based Binary-to-RNS Converter Modulo ${\{2^{n}{\pm}k\}}$ for $jn$ -bit Dynamic Range

Publication Year: 2015, Page(s):603 - 607
Cited by:  Papers (3)
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In this brief, a read-only-memoryless structure for binaryto-residue number system (RNS) conversion modulo (2n ±k} is proposed. This structure is based only on adders and constant multipliers. This brief is motivated by the existing (2n ± k} binary-to-RNS converters, which are particular inefficient for larger values of n. The experimental results obtained for 4... View full abstract»

• IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

Publication Year: 2015, Page(s): 608
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• IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2015, Page(s): C3
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu