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IEEE Journal of Solid-State Circuits

Issue 5 • Date May 1994

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Displaying Results 1 - 15 of 15
  • An automatic offset compensation scheme with ping-pong control for CMOS operational amplifiers

    Publication Year: 1994, Page(s):601 - 610
    Cited by:  Papers (38)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (948 KB)

    An automatic offset compensation scheme for CMOS operational amplifiers is presented. Offset is reduced by digitally adjusting the bias voltage of a programmable current mirror which is used as the load of the differential input stage. A 100% operating duty cycle is obtained by using a ping-pong structure. The offset compensation scheme is inherently time and temperature stable since the offset co... View full abstract»

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  • Amorphous silicon shift register for addressing output drivers

    Publication Year: 1994, Page(s):596 - 600
    Cited by:  Papers (22)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    An amorphous silicon (a-Si) shift register is described. By integrating this shift register design with an array of a-Si drivers, the cost/complexity of the interface to the array is significantly reduced, without trading off speed. Circuit design considerations unique to a-Si devices are also discussed along with their processing View full abstract»

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  • A 50 GHz broad-band monolithic GaAs/AlAs resonant tunneling diode trigger circuit

    Publication Year: 1994, Page(s):585 - 595
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    This paper describes the design, circuit simulation, fabrication and testing of a 50 GHz trigger circuit using GaAs/AlAs resonant tunneling diodes. A new trigger circuit was designed to eliminate the 180° phase splitter used in a previous complementary input trigger circuit. Our monolithic approach, integrated GaAs/AlAs resonant tunneling diodes (in a back-to-back configuration) and a 50 &Omeg... View full abstract»

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  • A concurrent error detection IC in 2-μm static CMOS logic

    Publication Year: 1994, Page(s):580 - 584
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    When a comprehensive fault model is considered, static CMOS VLSI has long been prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog faults (bridging and stuck-on faults). In this paper, we present the design, fabrication and testing of an experimental chip containing the integration of a totally self-checking (TSC) Berger code checker and a strongly code dis... View full abstract»

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  • Low-voltage, low-power BiCMOS digital circuits

    Publication Year: 1994, Page(s):572 - 579
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low ... View full abstract»

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  • A closed-form delay expression for digital BiCMOS circuits with high-injection effects

    Publication Year: 1994, Page(s):640 - 643
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    A non-iterative formula is derived for calculating the delay time of digital BICMOS circuits with their bipolar transistors operating in high-current regime. Effects such as the base transit-time increase of minority carriers and the decrease of the current gain of the bipolar transistors are all incorporated in the model. This model can be used to investigate the effects of most device parameters... View full abstract»

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  • Analysis and optimization of BiCMOS gate circuits

    Publication Year: 1994, Page(s):564 - 571
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B√F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit d... View full abstract»

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  • A CMOS floating-point vector-arithmetic unit

    Publication Year: 1994, Page(s):634 - 639
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine, hyperbolic (co)sine, square root, natural logarithm, inverse (hyperbolic) tangent, vector norm, and phase. The chip has been integrated in 1.6 μm double-metal n-well CMOS technology and achieves a ... View full abstract»

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  • BiCMOS circuit technology for a 704 MHz ATM switch LSI

    Publication Year: 1994, Page(s):557 - 563
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using t... View full abstract»

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  • Systematic capacitance matching errors and corrective layout procedures

    Publication Year: 1994, Page(s):611 - 616
    Cited by:  Papers (88)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    Precise capacitor ratios are employed in a variety of analog and mixed signal integrated circuits. The use of identical unit capacitors to form larger capacitances can easily produce 1% accuracy, but, in many cases, 0.1% accuracy can provide important performance advantages. Unfortunately, the ultimate matching precision of the ratio is limited by a number of systematic and random error sources. W... View full abstract»

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  • GaAs split phase dynamic logic

    Publication Year: 1994, Page(s):617 - 622
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large outp... View full abstract»

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  • A multiple-dimensional multiple-state SRAM cell using resonant tunneling diodes

    Publication Year: 1994, Page(s):623 - 630
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Several designs are presented for a multiple-dimensional multiple-state SRAM cell based on resonant tunneling diodes (RTDs). The proposed cells take advantages of the hysteresis and folding I-V characteristics of the RTD. When properly biased, the cell can operate up to (N+1)m or more number of stable quantized operating states, where N is the number of current-peaks of the RTD and m is... View full abstract»

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  • A silicon-bipolar amplifier for 10 Gbit/s with 45 dB gain

    Publication Year: 1994, Page(s):551 - 556
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    A 10 Gbit/s limiting main amplifier for use in optical transmission systems was implemented in an advanced 0.4 μm silicon-bipolar technology. The device has one differential input and two differential outputs. It is mounted and bonded on a softboard carrier for all of the following measurements. The small signal differential gain is 45 dB and the bandwidth is 9 GHz. The output voltage is limite... View full abstract»

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  • NCMOS: a high performance CMOS logic

    Publication Year: 1994, Page(s):631 - 633
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    CMOS has been the mainstay technology for VLSI design for the last several years. However, recently, BiCMOS technology has been proposed for speed critical applications. In this paper we propose a new circuit structure called NCMOS, which employs a low Vt NMOS transistor in place of the bipolar transistor, and provides significantly higher speed than a conventional CMOS design. This is realized at... View full abstract»

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  • High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology

    Publication Year: 1994, Page(s):546 - 550
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    We have designed and fabricated a high-bit-rate, high-input-sensitivity decision circuit for future optical communication systems using an advanced super self-aligned Si bipolar process technology (SST-1C). The SST-1C transistors are fabricated by 0.5-μm photolithography. The peak cut-off frequency of a typical transistor is 31 GHz at a collector-emitter voltage of 3 V. The circuit design invol... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com