# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 27

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2015, Page(s): C2
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• ### Editorial

Publication Year: 2015, Page(s):1 - 17
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• ### Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications

Publication Year: 2015, Page(s):18 - 29
Cited by:  Papers (2)
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The dedicated short-range communication (DSRC) is an emerging technique to push the intelligent transportation system into our daily life. The DSRC standards generally adopt FM0 and Manchester codes to reach dc-balance, enhancing the signal reliability. Nevertheless, the coding-diversity between the FM0 and Manchester codes seriously limits the potential to design a fully reused VLSI architecture ... View full abstract»

• ### Signal Processing With Direct Computations on Compressively Sensed Data

Publication Year: 2015, Page(s):30 - 43
Cited by:  Papers (10)
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Sparsity is characteristic of a signal that potentially allows us to represent information efficiently. We present an approach that enables efficient representations based on sparsity to be utilized throughout a signal processing system, with the aim of reducing the energy and/or resources required for computation, communication, and storage. The representation we focus on is compressive sensing. ... View full abstract»

• ### A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme

Publication Year: 2015, Page(s):44 - 53
Cited by:  Papers (3)
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This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035 mm2, making it suitable to embedding in VLSI systems, e.g., field-programmable gate array (FPGA). To cope with the IC process variability, a unit element approac... View full abstract»

• ### Design Techniques to Improve Blocker Tolerance of Continuous-Time $\Delta\Sigma$ ADCs

Publication Year: 2015, Page(s):54 - 67
Cited by:  Papers (6)
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Design techniques to provide robustness against loop saturation due to blockers in ΣA modulators are presented. Loop overload detection and correction are employed to improve the analog-to-digital converters (ADCs) tolerance to strong blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADCs blocker tolerance, a minim... View full abstract»

• ### Protein Alignment Systolic Array Throughput Optimization

Publication Year: 2015, Page(s):68 - 77
Cited by:  Papers (3)
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Protein comparison is gaining importance year after year since it has been demonstrated that biologists can find correlation between different species, or genetic mutations that can lead to cancer and genetic diseases. Protein sequence alignment is the most computational intensive task when performing protein comparison. To speed-up alignment, dedicated processors that can perform different comput... View full abstract»

• ### Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block

Publication Year: 2015, Page(s):78 - 87
Cited by:  Papers (2)
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In this paper, we propose a reliable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). The proposed ANT architecture can meet the demand of high precision, low power consumption, and area efficiency. We design the fixed-width RPR with error compensation circuit via ana... View full abstract»

• ### Efficient Hardware Architecture of $\eta_{T}$ Pairing Accelerator Over Characteristic Three

Publication Year: 2015, Page(s):88 - 97
Cited by:  Papers (1)
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To support emerging pairing-based protocols related to cloud computing, an efficient algorithm/hardware codesign methodology of ηT pairing over characteristic three is presented. By mathematical manipulation and hardware scheduling, a single Miller's loop can be executed within 17 clock cycles. Furthermore, we employ torus representation and exploit the Frobenius map to lower the computatio... View full abstract»

• ### An Ultralow Power Multirate FSK Demodulator With Digital-Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers

Publication Year: 2015, Page(s):98 - 106
Cited by:  Papers (2)
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An ultralow power (ULP), multirate frequency shift keying (FSK) demodulator applied for high-speed biomedical zero-IF receivers is presented. A digital-assisted calibrated delay-line (DL) based phase shifter is used for realizing multirate and low jitter demodulation under reported highest data rate. All circuits are operated in subthreshold region for achieving ULP consumption. Moreover, the powe... View full abstract»

• ### A Ripple Control Dual-Mode Single-Inductor Dual-Output Buck Converter With Fast Transient Response

Publication Year: 2015, Page(s):107 - 117
Cited by:  Papers (3)
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A novel integrated single-inductor dual-output buck converter based on the ripple control technique is presented, which can provide two independent output voltages (1.2 and 1.8 V) only using one inductor. The peak current common-mode and ripples compare differential-mode are adopted to improve the system transient response. The converter can automatically switch between pulsewidth modulation and p... View full abstract»

• ### A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures

Publication Year: 2015, Page(s):118 - 130
Cited by:  Papers (5)
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Electromigration (EM) has become a major power grid reliability problem in VLSI. In this paper, we first demonstrate that EM reliability analysis of a power grid can be converted to analyzing EM reliability of the grid vias. We develop a model for calculating EM lifetime of via-arrays and observe that making power grid EM-immortal carries a huge metal area overhead and possibly makes routing of bo... View full abstract»

• ### Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline

Publication Year: 2015, Page(s):131 - 141
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Miniaturization of very large scale integration circuits, higher frequencies and reduction of supply voltages make embedded systems more susceptible to soft errors (or transient errors). Soft errors affect the processor's pipeline and hence its data and control flows. Specifically, errors in control flows can change program's execution sequence, which might be catastrophic for safety-critical appl... View full abstract»

• ### Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

Publication Year: 2015, Page(s):142 - 155
Cited by:  Papers (2)
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As VLSI technology continuously scales down, buffered clock tree synthesis (CTS) has become increasingly critical in an attempt to generate a high-performance synchronous chip design. This paper presents a novel obstacle-avoiding CTS approach with slew constraints satisfied and signal polarity corrected. We build a look-up table through NGSPICE simulation to achieve accurate buffer delay and slew,... View full abstract»

• ### Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint

Publication Year: 2015, Page(s):156 - 169
Cited by:  Papers (5)
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Optical networks-on-chip (ONoCs) have shown the potential to be substituted for electronic networks-on-chip (NoCs) to bring substantially higher bandwidth and more efficient power consumption in both onand off-chip communication. However, basic optical devices, which are the key components in constructing ONoCs, experience inevitable crosstalk noise and power loss; the crosstalk noise from the bas... View full abstract»

• ### Aurora: A Cross-Layer Solution for Thermally Resilient Photonic Network-on-Chip

Publication Year: 2015, Page(s):170 - 183
Cited by:  Papers (2)
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With silicon optical technology moving toward maturity, the use of photonic networks-on-chip (NoCs) for global chip communication is emerging as a promising solution to the communication requirements of future many core processors. It is expected that photonic NoCs will play an important role in alleviating current power, latency, and bandwidth constraints. However, photonic NoCs are sensitive to ... View full abstract»

• ### A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2–10.1 GHz PLL

Publication Year: 2015, Page(s):184 - 188
Cited by:  Papers (1)
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This brief presents a wide-range multiport LC-ladder resonator and its application to phase-locked loop (PLL). The multiport LC-ladder structure provides a high-order resonator, which has multiple resonance frequencies. The output frequency can be discretely altered from these resonance frequencies through enabling or disabling the active devices of various ports. The capacitor bank provides conti... View full abstract»

• ### Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing

Publication Year: 2015, Page(s):189 - 193
Cited by:  Papers (4)
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Fault tolerant techniques can extend the power savings achievable by dynamic voltage scaling by trading accuracy and/or timing performance against power. Such energy improvements have a strong dependency on the delay distribution of the circuit and the statistical characteristics of the input signal. Independently, programmable truncated multipliers also achieve power benefits at the expense of de... View full abstract»

• ### A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler

Publication Year: 2015, Page(s):194 - 197
Cited by:  Papers (5)
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A high-speed CMOS TSPC divide-by-16/17 dual modulus prescaler is proposed. The speed of the prescaler is improved in two aspects. First, by adopting a new pseudo divide-by-2/3 prescaler, the minimum working period is effectively reduced by half a NOR gate's delay. Second, by changing the connection of TSPC D-Flip-Flops, the minimum working period is further reduced by half an inverter's delay. Sim... View full abstract»

• ### A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain

Publication Year: 2015, Page(s):198 - 202
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A process-variation resilient current mode logic (CML) is presented. The proposed CML employs time-reference-based adaptive biasing chain with replica load to address performance degradation over the process variations. It adjusts variable load resistor to simultaneously regulate time constant, voltage swing, level shifting, and DC gain. The prototype demonstrates the process-variation resiliency ... View full abstract»

• ### An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability

Publication Year: 2015, Page(s):203 - 207
Cited by:  Papers (6)
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This brief proposes an accuracy-adjustment fixed-width Booth multiplier that compensates the truncation error using a multilevel conditional probability (MLCP) estimator and derives a closed form for various bit widths L and column information w. Compared with the exhaustive simulations strategy, the proposed MLCP estimator substantially reduces simulation time and easily adjusts accuracy based on... View full abstract»

• ### Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection

Publication Year: 2015, Page(s):208 - 212
Cited by:  Papers (1)
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In this brief, we have proposed a design strategy for an energy-efficient circuit/architecture to detect the onset of epileptic seizures with high efficacy. The architecture consists of two stages. The first stage is a low complexity Coastline parameter algorithm that consumes very low energy per computation. The second stage is a more efficacious wavelet-based algorithm (discrete wavelet transfor... View full abstract»

• ### Recursive Approach to the Design of a Parallel Self-Timed Adder

Publication Year: 2015, Page(s):213 - 217
Cited by:  Papers (1)
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This brief presents a parallel single-rail self-timed adder. It is based on a recursive formulation for performing multibit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is pr... View full abstract»

Publication Year: 2015, Page(s):218 - 219
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu