# IEEE Transactions on Circuits and Systems I: Regular Papers

## Filter Results

Displaying Results 1 - 25 of 40

Publication Year: 2015, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

Publication Year: 2015, Page(s): C2
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• ### A Sub-$\mu{\rm W}$ Bandgap Reference Circuit With an Inherent Curvature-Compensation Property

Publication Year: 2015, Page(s):1 - 9
Cited by:  Papers (19)
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A new current-mode bandgap reference circuit (BGR) which is capable of generating sub-1-V output voltage is presented. It has not only the lowest theoretical minimum current consumption among published current-mode BGRs, but also additional advantages of an inherent curvature-compensation function and not requiring NPN BJTs. The curvature-compensation is achieved by utilizing the exponential behav... View full abstract»

• ### A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS

Publication Year: 2015, Page(s):10 - 18
Cited by:  Papers (13)
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This paper presents a 12-bit energy-efficient successive approximation register analog-to-digital converter (ADC). By incorporating the proposed capacitor-swapping technique, which eliminates the problematic MSB mismatch transition of a binary-weighted capacitor digital-to-analog converter, the 12-bit linearity of the ADC is achieved without increasing the capacitor size for improved matching. The... View full abstract»

• ### Distortion Analysis Using Volterra Series and Linearization Technique of Nano-Scale Bulk-Driven CMOS RF Amplifier

Publication Year: 2015, Page(s):19 - 28
Cited by:  Papers (6)
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The distortion analysis of nano-scale bulk-driven (BD) CMOS RF amplifier is presented based on Volterra series. The first three-order Volterra kernels are computed; and the closed-form expressions of the second-order and third-order harmonic distortion (HD) are derived. These expressions give good accuracy comparing with the simulation results, and can provide insight into the nonlinearity of nano... View full abstract»

• ### A Low Power Double-Sampling Extended Counting ADC With Class-AB OTA for Sensor Arrays

Publication Year: 2015, Page(s):29 - 38
Cited by:  Papers (4)
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Due to its high resolution, small silicon area, and reasonable conversion rate, extended counting analog to digital conversion (EC-ADC) has become a competitive candidate for application in the readout circuits of high accuracy sensors. In this paper, an EC-ADC for large scale sensor arrays is proposed. At the system level, a double-sampling configuration for incremental ΣΔ modulator... View full abstract»

• ### Analog Circuit Design Using Tunnel-FETs

Publication Year: 2015, Page(s):39 - 48
Cited by:  Papers (26)
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Tunnel-FET (TFET) is a major candidate for beyond-CMOS technologies. In this paper, the properties of the TFETs that affect analog circuit design are studied. To demonstrate how TFETs can enhance the performance or change the topology of the analog circuits, several building blocks such as operational transconductance amplifiers (OTAs), current mirrors, and track-and-hold circuits are examined. It... View full abstract»

Publication Year: 2015, Page(s):49 - 58
Cited by:  Papers (9)
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A lookup-table digital correction technique using “split ADC” calibration is used for linearization of VCO-based ADCs. Simulation results in a 45 nm CMOS process targeting 10 b and 12 b resolutions show ENOB of 9.58 b and 11.5 b, with convergence times for background calibration adaptation of 380 ms and 5.7 s, respectively. The background LMS procedure is tolerant of different input ... View full abstract»

• ### A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement

Publication Year: 2015, Page(s):59 - 69
Cited by:  Papers (4)
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The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.... View full abstract»

• ### A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS

Publication Year: 2015, Page(s):70 - 79
Cited by:  Papers (16)
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This paper presents a 10-bit ultra-low voltage energy-efficient SAR ADC. The proposed merge-and-split (MS) switching effectively reduces DAC switching energy by 83% compared with conventional one without the need of extra reference voltage (Vcm) and the issue of common-mode voltage variation. To maintain good input linearity, a new double-bootstrapped sample-and-hold (S/H) circuit is proposed unde... View full abstract»

• ### A 2 mW, 50 dB DR, 10 MHz BW 5 $times$ Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF

Publication Year: 2015, Page(s):80 - 89
Cited by:  Papers (2)
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A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma (ΔΣ) modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a feed-forward topology. To further improve its power-efficiency, the ADC employs inverter-based OTAs with the help of auxiliary inverters for extra gain. A 0.55 mm2 c... View full abstract»

• ### A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference

Publication Year: 2015, Page(s):90 - 99
Cited by:  Papers (7)
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Sub-sampling phase detectors (SSPDs) have recently been demonstrated to enable phase-locked loop (PLL) realizations with very low in-band noise. However, the PLL becomes susceptible to disturbances or interference via substrate or power supply coupling as experienced in systems on chip (SOCs), which could put the PLL out of lock. A tri-state phase-frequency detector with a dead-zone is traditional... View full abstract»

• ### An Architecture With Pipelined Background Suppression and In-Situ Noise Cancelling for 2D/3D CMOS Image Sensor

Publication Year: 2015, Page(s):100 - 109
Cited by:  Papers (3)
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We present a CMOS image sensor with integrated background suppression scheme for detecting small signals out of unwanted background signals. For the background suppression, differential signals with suppressed common-mode background signals are sampled within a short sub-sensing time in order to avoid the saturation from strong background signals. Analog differential signals are digitally accumula... View full abstract»

• ### High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations

Publication Year: 2015, Page(s):110 - 119
Cited by:  Papers (6)
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Redundant basis (RB) multipliers over Galois Field ( GF(2m)) have gained huge popularity in elliptic curve cryptography (ECC) mainly because of their negligible hardware cost for squaring and modular reduction. In this paper, we have proposed a novel recursive decomposition algorithm for RB multiplication to obtain high-throughput digit-serial implementation. Through efficient projectio... View full abstract»

• ### SEA-SSD: A Storage Engine Assisted SSD With Application-Coupled Simulation Platform

Publication Year: 2015, Page(s):120 - 129
Cited by:  Papers (2)
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A storage engine assisted solid-state drive (SEA-SSD) has been proposed to improve the write performance of the SSDs for database applications. Since the SSD write performance bottleneck is caused by the garbage collection, the motivation of this work is to reduce the SSD garbage collection overhead by identifying, clustering and aggregating the data with similar activity in the same block of the ... View full abstract»

• ### Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator

Publication Year: 2015, Page(s):130 - 138
Cited by:  Papers (8)
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In this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 × 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA... View full abstract»

• ### BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems

Publication Year: 2015, Page(s):139 - 148
Cited by:  Papers (11)
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This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan switch network (SSN) architecture is proposed to perform pre-bond TSV scan testing in test mode, and operate as functional circuit in functional mode, respectively. In t... View full abstract»

• ### DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes

Publication Year: 2015, Page(s):149 - 156
Cited by:  Papers (10)
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Low-power mobile devices such as RFID tags and WSNs that employ AES cryptographic modules are susceptible to differential power analysis (DPA) attacks. This paper presents a novel secured quasi-adiabatic logic (SQAL) technology that is both low-power and DPA immune. The efficiency of the SQAL technology was evaluated on an 8-bit AES-128 SBOX block and proved to be robust against DPA attacks. Compa... View full abstract»

• ### High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems

Publication Year: 2015, Page(s):157 - 166
Cited by:  Papers (14)
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Polynomial multiplication is the basic and most computationally intensive operation in ring-learning with errors (ring-LWE) encryption and "somewhat" homomorphic encryption (SHE) cryptosystems. In this paper, the fast Fourier transform (FFT) with a linearithmic complexity of O(nlogn), is exploited in the design of a high-speed polynomial multiplier. A constant geometry FFT datapath is used in the ... View full abstract»

• ### A Sigma-Delta Domain Lowpass Wave Filter

Publication Year: 2015, Page(s):167 - 176
Cited by:  Papers (1)
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This paper presents a sigma-delta (SD) domain lowpass wave filter modeled after an analog distributed parameter filter (ADPF). The SD domain filter operating on SD modulated signals is built with two kinds of units, shift registers on which two-level-quantized waves propagate and sorter-based units that simulate reflection, transmission, and superposition of waves propagating on the transmission l... View full abstract»

• ### One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes

Publication Year: 2015, Page(s):177 - 184
Cited by:  Papers (11)
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A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, and propose efficient estimators to infer the second minimum value. By doing so, we greatly reduce the complexity and at the same time improve latency and throughput of the derived... View full abstract»

• ### An RLS Tracking and Iterative Detection Engine for Mobile MIMO-OFDM Systems

Publication Year: 2015, Page(s):185 - 194
Cited by:  Papers (5)
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This paper presents a tracking and detection engine for 2 × 2 spatial-multiplexing multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems under highly time-selective fading channels. A recursive least-squares (RLS) adaptive algorithm is adopted to track time-varying channel frequency response. Besides, iterative MIMO signal detection is used, including... View full abstract»

• ### Design of Sparse FIR Filters With Joint Optimization of Sparsity and Filter Order

Publication Year: 2015, Page(s):195 - 204
Cited by:  Papers (6)
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In this paper, two novel algorithms are developed to design sparse linear-phase (LP) FIR filters. Compared to traditional design methods, they can jointly optimize coefficient sparsity and order of an LP FIR filter, so as to achieve a balance between filtering performance and implementation efficiency. The design problem under consideration is formally cast as a regularized l0-norm mini... View full abstract»

• ### Towards Analog Memristive Controllers

Publication Year: 2015, Page(s):205 - 214
Cited by:  Papers (2)
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Memristors, initially introduced in the 1970s, have received increased attention upon successful synthesis in 2008. Considerable work has been done on modeling and applications in specific areas, however, very little is known on the potential of memristors for control applications. Being nanoscopic variable resistors, it is intuitive to think of using them as a variable gain. The main contribution... View full abstract»

• ### A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses

Publication Year: 2015, Page(s):215 - 223
Cited by:  Papers (24)
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Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK