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Computer

Issue 7 • July 1988

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Displaying Results 1 - 5 of 5
  • Formal verification of hardware correctness: introduction and survey of current research

    Publication Year: 1988, Page(s):8 - 19
    Cited by:  Papers (56)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1436 KB)

    Formal verification techniques are analyzed, focusing on two key points: suitable representation systems and mechanizable proofs. Different approaches to hardware verification are first examined, and formal verification and automated synthesis are compared to show how they cooperate in producing zero-defect designs. The different techniques are evaluated. Cross fertilization with software verifica... View full abstract»

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  • An exercise in plausibility-driven design

    Publication Year: 1988, Page(s):21 - 31
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (883 KB)

    The authors describe an evolutionary model of the computer design process and introduce the concept of plausibility of a design, which depends on the history of the design, where history refers to the recorded sequences of design decisions and the cause-effect relationships between design decisions, and the nature of the evidence used by the designer to justify design decisions and/or establish th... View full abstract»

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  • Lisp on a reduced-instruction-set processor: characterization and optimization

    Publication Year: 1988, Page(s):34 - 45
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1090 KB)

    The factors that motivated the choice of a reduced-instruction-set computer (RISC) on which to implement Lisp are examined. Dynamic profiling measurements used to characterise Lisp are reported. The implementation of tags in Lisp and the cost of function calls are discussed. Interprocedural register allocation is examined. Execution results for various benchmarks are presented and discussed.... View full abstract»

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  • Reducing the branch penalty in pipelined processors

    Publication Year: 1988, Page(s):47 - 55
    Cited by:  Papers (51)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    A probabilistic model is developed to quantify the performance effects of the branch penalty in a typical pipeline. The branch penalty is analyzed as a function of the relative number of branch instructions executed and the probability that a branch is taken. The resulting model shows the fraction of maximum performance achievable under the given conditions. Techniques to reduce the branch penalty... View full abstract»

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  • The Open Channel

    Publication Year: 1988, Page(s):59 - 60
    Cited by:  Papers (4)
    Request permission for commercial reuse | PDF file iconPDF (182 KB)
    Freely Available from IEEE

Aims & Scope

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed articles written for and by computer researchers and practitioners representing the full spectrum of computing and information technology, from hardware to software and from emerging research to new applications. 

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Editor-in-Chief
Sumi Helal
Lancaster University
sumi.helal@computer.org