IEEE Computer Architecture Letters

Issue 2 • July-Dec. 2014

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Displaying Results 1 - 18 of 18
  • Table of Contents

    Publication Year: 2014, Page(s): C1
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  • IEEE Computer Architecture Letters Editorial Board

    Publication Year: 2014, Page(s): C2
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  • An FPGA-based In-Line Accelerator for Memcached

    Publication Year: 2014, Page(s):57 - 60
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1987 KB) | HTML iconHTML

    We present a method for accelerating server applications using a hybrid CPU+FPGA architecture and demonstrate its advantages by accelerating Memcached, a distributed key-value system. The accelerator, implemented on the FPGA fabric, processes request packets directly from the network, avoiding the CPU in most cases. The accelerator is created by profiling the application to determine the most comm... View full abstract»

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  • Architecting Flash-based Solid-State Drive for High-performance I/O Virtualization

    Publication Year: 2014, Page(s):61 - 64
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (721 KB) | HTML iconHTML

    Flash-based solid-state drive (SSD) is now being widely deployed in cloud computing platforms due to the potential advantages of better performance and less energy consumption. However, current virtualization architecture lacks support for highperformance I/O virtualization over persistent storage, which results in sub-optimal I/O performance for guest virtual machines (VMs) on SSD. Further, curre... View full abstract»

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  • Architectural Thermal Energy Harvesting Opportunities for Sustainable Computing

    Publication Year: 2014, Page(s):65 - 68
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (866 KB) | HTML iconHTML

    Increased power dissipation in computing devices has led to a sharp rise in thermal hotspots, creating thermal runaway. To reduce the additional power requirement caused by increased temperature, current approaches apply cooling mechanisms to remove heat or apply management techniques to avoid thermal emergencies by slowing down heat generation. This paper proposes to tackle the heat management pr... View full abstract»

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  • Cache Hierarchy Optimization

    Publication Year: 2014, Page(s):69 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3014 KB) | HTML iconHTML

    Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CMP cache hierarchy and optimally allocating area among hierarchy levels under such constrained resources is developed. The optimization framework is extended by incorpor... View full abstract»

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  • Coding Last Level STT-RAM Cache for High Endurance and Low Power

    Publication Year: 2014, Page(s):73 - 76
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7911 KB) | HTML iconHTML

    STT-RAM technology has recently emerged as one of the most promising memory technologies. However, its major problems, limited write endurance and high write energy, are still preventing it from being used as a drop-in replacement of SRAM cache. In this paper, we propose a novel coding scheme for STT-RAM last level cache based on the concept of value locality. We reduce switching probability in ca... View full abstract»

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  • Heuristics for Thread-Level Speculation in Web Applications

    Publication Year: 2014, Page(s):77 - 80
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (795 KB) | HTML iconHTML

    JavaScript is a sequential programming language, and Thread-Level Speculation has been proposed to dynamically extract parallelism in order to take advantage of parallel hardware. In previous work, we have showed significant speed-ups with a simple on/off speculation heuristic. In this paper, we propose and evaluate three heuristics for dynamically adapt the speculation: a 2-bit heuristic, an expo... View full abstract»

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  • On Optimal Kernel Size for Integrated CPU-GPUs — A Case Study

    Publication Year: 2014, Page(s):81 - 84
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5164 KB) | HTML iconHTML

    Integrated CPU-GPU architectures with a fully addressable shared memory completely eliminate any CPU-GPU data transfer overhead. Since such architectures are relatively new, it is unclear what level of interaction between the CPU and GPU attains the best energy efficiency. Too coarse grained or larger kernels with fairly low CPU - GPU interaction could cause poor utilization of the shared resource... View full abstract»

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  • Per-task Energy Accounting in Computing Systems

    Publication Year: 2014, Page(s):85 - 88
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB) | HTML iconHTML

    We present for the first time the concept of per-task energy accounting (PTEA) and relate it to per-task energy metering (PTEM). We show the benefits of supporting both in future computing systems. Using the shared last-level cache (LLC) as an example: (1) We illustrate the complexities in providing PTEM and PTEA; (2) we present an idealized PTEM model and an accurate and low-cost implementation o... View full abstract»

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  • Resistive Computation: A Critique

    Publication Year: 2014, Page(s):89 - 92
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2090 KB) | HTML iconHTML

    Resistive Computation was suggested by [6] as an idea for tacking the power wall by replacing conventional CMOS logic with Magnetic Tunnel Junction (MTJ) based Look-Up Tables (LUTs). Spin Transfer Torque RAM (STTRAM) is an emerging CMOS-compatible non-volatile memory technology based on Magnetic Tunnel Junctions as a memory bit [3]. The principal advantage of STTRAM is that it is leakage-resistant... View full abstract»

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  • Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance

    Publication Year: 2014, Page(s):93 - 96
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB) | HTML iconHTML

    Weighted speedup is nowadays the most commonly used multiprogram workload performance metric. Weighted speedup is a weighted-IPC metric, i.e., the multiprogram IPC of each program is first weighted with its isolated IPC. Recently, Michaud questions the validity of weighted-IPC metrics by arguing that they are inconsistent and that weighted speedup favors unfairness [4]. Instead, he advocates using... View full abstract»

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  • Revisiting Using the Results of Pre-Executed Instructions in Runahead Processors

    Publication Year: 2014, Page(s):97 - 100
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3463 KB) | HTML iconHTML

    Long-latency cache accesses cause significant performance-impacting delays for both in-order and out-of-order processor systems. To address these delays, runahead pre-execution has been shown to produce speedups by warming-up cache structures during stalls caused by long-latency memory accesses. While improving cache related performance, basic runahead approaches do not otherwise utilize results f... View full abstract»

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  • ScaleGPU: GPU Architecture for Memory-Unaware GPU Programming

    Publication Year: 2014, Page(s):101 - 104
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1411 KB) | HTML iconHTML

    Programmer-managed GPU memory is a major challenge in writing GPU applications. Programmers must rewrite and optimize an existing code for a different GPU memory size for both portability and performance. Alternatively, they can achieve only portability by disabling GPU memory at the cost of significant performance degradation. In this paper, we propose ScaleGPU, a novel GPU architecture to enable... View full abstract»

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  • Soft Failures in Large Datacenters

    Publication Year: 2014, Page(s):105 - 108
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3124 KB) | HTML iconHTML

    A major problem in managing large-scale datacenters is diagnosing and fixing machine failures. Most large datacenter deployments have a management infrastructure that can help diagnose failure causes, and manage assets that were fixed as part of the repair process. Previous studies identify only actual hardware replacements to calculate Annualized Failure Rate (AFR) and component reliability. In t... View full abstract»

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  • vCache: Providing a Transparent View of the LLC in Virtualized Environments

    Publication Year: 2014, Page(s):109 - 112
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (781 KB) | HTML iconHTML

    Since most of the current multi-core processors use a large last-level cache (LLC), efficient use of an LLC is critical for the overall performance of multi-cores. To improve the caching efficiency, page coloring is a representative software-based approach to allow the OS to control placement of pages on an LLC to improve their cache utility and to avoid conflicts among cores. However, system virt... View full abstract»

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  • IEEE Computer Architecture Letters Information for Authors

    Publication Year: 2014, Page(s): C3
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  • IEEE Computer Society [advertisement]

    Publication Year: 2014, Page(s): C4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Daniel J. Sorin
Duke University
Electrical & Computer Engineering
PO Box 90291
Durham, NC 27708
e-mail: sorin@ee.duke.edu