IEEE Transactions on Computers

Issue 5 • May 1994

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Displaying Results 1 - 15 of 15
  • Application of homing sequences to synchronous sequential circuit testing

    Publication Year: 1994, Page(s):569 - 580
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1184 KB)

    A test generation procedure for synchronous sequential circuits is proposed, that is based on the multiple observation times approach, and uses homing sequences, instead of conventionally used synchronizing sequences, to initialize the circuit. A procedure for computing homing sequences in sequential circuits, for which a state-table description is too large to be practical, is described, and expe... View full abstract»

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  • Decomposition of {0,1}-matrices

    Publication Year: 1994, Page(s):629 - 633
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    A simple decomposition of a r×c{0,1}-matrix is defined in terms of a collection of disjoint submatrices obtained by deleting a “minimal” set of columns. In general, the number of such simple decompositions is Θ(2r). A class of matrices, namely, vertex-tree graphic, is defined, and it is shown that the number of simple decompositions of a vertex-tree graphic matri... View full abstract»

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  • Salphasic distribution of clock signals for synchronous systems

    Publication Year: 1994, Page(s):597 - 602
    Cited by:  Papers (61)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    The design of a synchronous system having a global clock must account for propagation-delay-induced phase shifts experienced by the clock signal (clock skew) in its distribution network. As clock speeds and system diameters increase, this requirement becomes increasingly constraining on system designs. The paper describes a method that exploits properties of standing waves to reduce substantially ... View full abstract»

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  • Maximal and near-maximal shift register sequences: efficient event counters and easy discrete logarithms

    Publication Year: 1994, Page(s):560 - 568
    Cited by:  Papers (18)  |  Patents (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    A linear feedback shift register, or LFSR, can implement an event counter by shifting whenever an event occurs. A single two-input exclusive-OR gate is often the only additional hardware necessary to allow a shift register to generate, by successive shifts, all of its possible nonzero values. The counting application requires that the number of shifts be recoverable from the LFSR contents so that ... View full abstract»

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  • Digit-set conversions: generalizations and applications

    Publication Year: 1994, Page(s):622 - 629
    Cited by:  Papers (43)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    The problem of digit set conversion for fixed radix is investigated for the case of converting into a non redundant, as well as into a redundant, digit set. Conversion may be from very general digit sets, and covers as special cases multiplier recodings, additions, and certain multiplications. We generalize known algorithms for conversions into non redundant digit sets, as well as apply conversion... View full abstract»

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  • Asymmetric/unidirectional error correcting and detecting codes

    Publication Year: 1994, Page(s):590 - 597
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    Introduces the theory and design of codes that correct t asymmetric errors and simultaneously detect d(d>t) asymmetric errors (t-AEC/d-AED). These codes have a much higher information rate than symmetric error correcting/detecting codes and yet maintain the same encoding and decoding complexity as existing error correcting codes. They are suited for asymmetric channels such as digital transmiss... View full abstract»

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  • Wiring knock-knee layouts: a global approach

    Publication Year: 1994, Page(s):581 - 589
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (820 KB)

    Presents a global approach to solve the three-layer wirability problem for knock-knee layouts. In general, the problem is NP-complete. Only for very restricted classes of layouts polynomial three-layer wiring algorithms are known up to now. The authors show that for a large class of layouts a three-layer wiring can be constructed by solving a path problem in a special class of graphs or a two-sati... View full abstract»

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  • Identifying minimal shift counters: a search technique

    Publication Year: 1994, Page(s):633 - 639
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    A minimal modulo-m n-stage shift counter is defined as a shift counter with a feedback function of the form Y1=yn$ View full abstract»

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  • Fast parallel algorithm for ternary multiplication using multivalued I2L technology

    Publication Year: 1994, Page(s):603 - 607
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Presents an algorithm for parallel multiplication of two n-bit ternary numbers. This algorithm uses the technique of column compression and computes the product in (2 upper bound [log2n]+2) units of addition time of a single-bit ternary full adder. This algorithm requires regular interconnection between any two types of cells and hence is very suitable for VLSI implementation. The same ... View full abstract»

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  • Logically instantaneous message passing in asynchronous distributed systems

    Publication Year: 1994, Page(s):513 - 527
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1352 KB)

    Asynchrony (due to unknown message transmission delay) complicates the design of protocols for distributed systems. To simplify the protocol design task therefore, the authors propose an interprocess (point-to-point) communication mechanism that has the characteristic of instantaneous message passing. They first establish a hierarchy among synchronization properties, which shows that to ensure the... View full abstract»

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  • Embedding of rings and meshes onto faulty hypercubes using free dimensions

    Publication Year: 1994, Page(s):608 - 613
    Cited by:  Papers (52)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    Fault tolerance in hypercubes is achieved by exploiting inherent redundancy and executing tasks on faulty hypercubes. The authors consider tasks that require linear chain, ring, mesh, and torus structure, which are quite useful in parallel and pipeline computations. They assume the number of faults is on the order of the number of dimensions of the hypercube. The techniques are based on a key conc... View full abstract»

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  • Incorporation of optimal timeouts into distributed real-time load sharing

    Publication Year: 1994, Page(s):528 - 547
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1680 KB)

    Consideration is given to the problem of designing and incorporating a timeout mechanism into load sharing (LS) with state-region change broadcasts in the presence of node failures in a distributed real-time system. Failure of a node is diagnosed by the other nodes through communication timeouts, and the timeout period used to diagnose whether a node is faulty or not usually depends on the dynamic... View full abstract»

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  • Assignment of task modules in hypercube multicomputers with component failures for communication efficiency

    Publication Year: 1994, Page(s):613 - 618
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    The problem of assigning task modules within a hypercube multicomputer with possible link failures is investigated. A concept of indirect optimization is introduced and a function, called communication traffic, is proposed as the objective of optimization. The assignments obtained from optimizing this function are shown to significantly improve the actual communication performance measure, called ... View full abstract»

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  • A nonblocking algorithm for shared queues using compare-and-swap

    Publication Year: 1994, Page(s):548 - 559
    Cited by:  Papers (22)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    Nonblocking algorithms for concurrent objects guarantee that an object is always accessible, in contrast to blocking algorithms in which a slow or halted process can render part or all of the data structure inaccessible to other processes. A number of algorithms have been proposed for shared FIFO queues, but nonblocking implementations are few and either limit the concurrency or provide inefficien... View full abstract»

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  • A multiaccess frame buffer architecture

    Publication Year: 1994, Page(s):618 - 622
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Many current graphical display systems are based around a memory array commonly known as a frame buffer. In these systems, the frame buffer contains the array of pixels currently being displayed. Updates to the display are accomplished by modifying the values in the frame buffer. The author demonstrates how the performance of frame buffer based systems can be improved by decreasing the number of a... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org