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Solid-State Circuits, IEEE Journal of

Issue 4 • Date Apr 1994

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Displaying Results 1 - 22 of 22
  • Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

    Page(s): 454 - 460
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low Vcc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm2 and the chip measures 5.8×5.0 mm 2. The divided bit line structure realizes a small NOR type memory cell View full abstract»

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  • A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation

    Page(s): 461 - 469
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB)  

    A 16-Mb flash EEPROM has been developed based on the 0.6-μm triple-well double-poly-Si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to overcome the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 μm×1.7 μm, resulting in a die size of 7.7 mm×17.32 mm View full abstract»

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  • Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment

    Page(s): 470 - 480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (852 KB)  

    This paper describes low-voltage and low-power (LV/LP) circuit design for both analog LSI's and digital LSI's which are used in mixed analog/digital systems in portable equipment. We review some LV/LP circuits used in digital LSI's, such as general logic gate, DSP, and DRAM, and others used in analog LSI's, such as operational amplifiers, video-signal processing circuits, A/D and D/A converters, filters, and RF circuits, along with a wide range of items used in recently developed LSI's. Since analog circuits have fundamental difficulties in reducing the operating voltage and the power consumption, in spite of recent progress in LV/LP circuit techniques, these difficulties will be a major issue for decreasing the total power consumption of some mixed analog/digital systems used in portable equipment View full abstract»

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  • The role of VLSI in multimedia

    Page(s): 381 - 388
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    The opportunity to develop multimedia applications based on compressed video is the result of progress in three areas: standards, networking, and VLSI. Current video coding standards and their underlying algorithms use a variety of techniques to isolate and remove redundancies in the image sequence. Some of these techniques place severe demands on the underlying VLSI technology. Manufacturers of VLSI codecs have chosen a number of different architectural approaches. The advantages and disadvantages of each are discussed in the context of various applications with examples taken from existing or soon to be announced products. The AT&T AVP4000 chip set is described in some detail. Major design challenges included CAD tools for simulation and verification, packaging and the control of power dissipation View full abstract»

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  • A stereo asynchronous digital sample-rate converter for digital audio

    Page(s): 481 - 488
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    The design of an asynchronous digital sample-rate converter for digital-audio applications is presented. The theory of asynchronous sample-rate conversion is discussed using a signal-processing model that is based on highly interpolated input samples. A novel closed-loop address-tracking system is disclosed that solves the problem of clock-edge arrival estimation while at the same time providing a low-jitter selection of the correct polyphase filter for each output sample. Sample-rate ratio changes of up to 2:1 in either direction can be accommodated. The proposed signal-processing algorithm has been implemented in a 0.8-μm CMOS technology. Measurement results show excellent agreement with theory View full abstract»

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  • A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage read channels

    Page(s): 489 - 499
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    A monolithic active equalizer in 2-μm CMOS technology is described, suitable for use in magnetic storage read channels employing peak-detection. Computer simulation of the channel and numerical optimization of equalizer performance have led to a 4-pole equalizer which outperforms conventional 7-pole linear-phase pulse-slimming equalizers. Circuits with matched and scaled stray capacitances use low transconductance amplifiers, with a total on-chip power dissipation of 40 mW (excluding output buffers). A master-slave architecture tunes filter pole frequencies and quality factors (Q) to their nominal values against process and temperature variations View full abstract»

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  • A 120-MHz BiCMOS superscalar RISC processor

    Page(s): 389 - 396
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    A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm×16.5 mm, and utilizes 3.3 V/0.5 μm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design View full abstract»

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  • A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

    Page(s): 411 - 418
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    A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved View full abstract»

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  • Standby/active mode logic for sub-1-V operating ULSI memory

    Page(s): 441 - 447
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    New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-μA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic View full abstract»

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  • Open/folded bit-line arrangement for ultra-high-density DRAM's

    Page(s): 539 - 542
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F2 memory cell, where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement View full abstract»

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  • A 700-MHz switched-capacitor analog waveform sampling circuit

    Page(s): 500 - 508
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB)  

    Analog switched-capacitor memory circuits are suitable for use in a wide range of applications where analog waveforms must be captured or delayed, such as the recording of pulse echo events and pulse shapes. Analog sampling systems based on switched-capacitor techniques offer performance superior to that of flash A/D converters and charge-coupled devices with respect to cost, density, dynamic range, sampling speed, and power consumption. This paper proposes an architecture with which sampling frequencies of several hundred megahertz can be achieved using conventional CMOS technology. Issues concerning the design and implementation of an analog memory circuit based on the proposed architecture are presented. An experimental two-channel memory with 32 sampling cells in each channel has been integrated in a 2-μm CMOS technology with poly-to-poly capacitors. The measured nonlinearity of this prototype is 0.03% for a 2.5 V input range, and the memory cell gain matching is 0.01% rms. The dynamic range of the memory exceeds 12 b for a sampling frequency of 700 MHz. The power dissipation for one channel operated from a single +5 V supply is 2 mW View full abstract»

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  • A 110-MHz/1-Mb synchronous TagRAM

    Page(s): 403 - 410
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    A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation and clock to Dout of 4.7 ns are achieved by use of circuit techniques such as a pipelined decoding scheme, a single PMOS load BiCMOS main decoder, a BiCMOS sense-amplifying comparator, doubly placed self-timed write circuits, and highly linear VCO for a PLL. The device is successfully implemented with 0.7-μm double polysilicon double-metal BiCMOS technology View full abstract»

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  • A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits

    Page(s): 523 - 528
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    A feedback-controlled active-pull-down emitter follower that is self-biased at a low steady-state current and allows the collector dotting and emitter dotting is proposed for high-speed low-power bipolar/BiCMOS digital logic circuits. The push-pull operation of this emitter follower is precisely controlled by a feedback mechanism and does not require any extra out-of-phase signal other than the emitter-follower input from the logic stage. Simulation results based on a 0.5-μm advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively View full abstract»

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  • A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter

    Page(s): 516 - 522
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    A BiCMOS A/D converter using a “differential voltage subconverter,” which directly converts a voltage difference of complementary analog inputs to a digital code, is described. Fully differential architecture has advantages in immunity of common-mode error and in reduction of supply voltage. This differential-voltage subconverter realizes the fully differential A/D conversion without using interpolation technique. This subconverter is free from CR delay caused in the ladder resistors. Circuit techniques for high-accuracy conversion with single 5-V power supply, such as compensation technique for VBE modulation in emitter degeneration amplifier, are also described. A 10-b A/D converter is fabricated in a 0.8-μm BiCMOS process with fT of 9 GHz. It successfully operates at 50 MS/s with 500-mW power consumption and with 5-V single supply View full abstract»

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  • 16-Mb synchronous DRAM with 125-Mbyte/s data rate

    Page(s): 529 - 533
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    In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M×8) achieves a 125-Mbyte/s data rate using 0.5-μm twin well CMOS technology View full abstract»

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  • A fuzzy logic inference processor

    Page(s): 397 - 402
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    A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 μm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 μs View full abstract»

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  • Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs

    Page(s): 448 - 453
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    A new reference voltage generator with ultralow standby current of less than 1 μA is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-μm process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm/°C from room temperature to 100°C, and output noise of less than 12 mV for 1 Vp-p Vcc bumping are achieved. These results are sufficient for achieving high-density battery operated DRAMs with low active and data-retention currents comparable to SRAMs View full abstract»

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  • A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs

    Page(s): 432 - 440
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    Proposes an advanced DRAM array driving technique which can achieve low-voltage operation, a well-synchronized sensing and equalizing method. This method sets the DRAM array free from the body effect, achieves a small influence of the short channel effect, and reduces the leakage current. The sense and restore amplifier and equalizer can operate rapidly under a low-voltage operating condition such as 1.0 V VCC. Therefore, one can make determining the V th easy for the satisfaction of the high-speed, the low-power dissipation, and a simple device structure. The well-synchronized sensing and equalizing method is applicable to low-voltage operating DRAMs with capacity of 256 Mbits and more View full abstract»

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  • A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates

    Page(s): 419 - 425
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    An 18-kb RAM with 9-kgate control logic gates operating during a cycle-time of 1.5 ns has been developed. A pseudo-dual-port RAM function is achieved by a two-bank structure and on-chip control logic. Each bank can operate individually with different address synchronizing the single clock. A sense-amplifier with a selector function reduces the reading propagation time. Bonded SOI wafers reduce the memory-cell capacitance, and this results in a fast write cycle without sacrificing α-particle immunity. The chip is fabricated in a double polysilicon self-aligned bipolar process using trench isolation. The minimum emitter size is 0.5×2 μm2 and the chip size is 11×11 mm2 View full abstract»

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  • An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

    Page(s): 534 - 538
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    An efficient back-bias (Vbb) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a Vbb level of -1.44 V at Vcc=1.5 V, compared to a conventional system in which Vbb only reaches -0.6 V. HPC can pump without the threshold voltage (Vth) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a Vbb level lower than -1.0 V is necessary to meet the limitations of the Vth, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection View full abstract»

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  • 250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

    Page(s): 426 - 431
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    A 3.3-V 512-k×18-b×2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm2, which is the same die size as the conventional DRAM, has been achieved with 0.50-μm CMOS process technology View full abstract»

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  • A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC

    Page(s): 509 - 515
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    This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-μm CMOS process. The ADC operates at 600 ks/s using 45 mW of power at ±2.5 V supplies. The active die area excluding the external logic circuit is 1 mm2. Maximum DNL of ±0.6 LSB and INL of ±1 LSB at a 12-b resolution have been achieved View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan