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IEEE Transactions on Computers

Issue 4 • April 1994

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Displaying Results 1 - 14 of 14
  • Comments on "Area-time optimal adder design"

    Publication Year: 1994, Page(s):507 - 512
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (409 KB)

    A previous paper by Wei and Thompson (1990) defined a family of adders based on a modular design and presented an excellent systematic method of implementing a VLSI parallel adder using three types of component cells designed in static CMOS. Their approach to the adder design was based on the optimization of a formulated dynamic programming problem with respect to area and time. The authors first ... View full abstract»

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  • Optimal parallel and pipelined processing through a new class of matrices with application to generalized spectral analysis

    Publication Year: 1994, Page(s):443 - 459
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1240 KB)

    A new class of general-base matrices, named sampling matrices, which are meant to bridge the gap between algorithmic description and computer architecture is proposed. “Poles,” “zeros,” “pointers,” and “spans” are among the terms introduced to characterize properties of this class of matrices. A formalism for the decomposition of a general matrix in ... View full abstract»

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  • Instruction window size trade-offs and characterization of program parallelism

    Publication Year: 1994, Page(s):431 - 442
    Cited by:  Papers (31)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1156 KB)

    Detecting independent operations is a prime objective for computers that are capable of issuing and executing multiple operations simultaneously. The number of instructions that are simultaneously examined for detecting those that are independent is the scope of concurrency detection. The authors present an analytical model for predicting the performance impact of varying the scope of concurrency ... View full abstract»

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  • Computational arrays with flexible redundancy

    Publication Year: 1994, Page(s):413 - 430
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1620 KB)

    Different multiple redundancy schemes for fault detection and correction in computational arrays are proposed and analyzed. The basic idea is to embed a logical array of nodes onto a processor/switch array such that d processors, 1⩽d⩽4, are dedicated to the computation associated with each node. The input to a node is directed to the d processors constituting that node, and the output of t... View full abstract»

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  • Testing iterative logic arrays for sequential faults with a constant number of patterns

    Publication Year: 1994, Page(s):495 - 501
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    Shows that a constant number of test vectors are sufficient for fully testing a k-dimensional ILA for sequential faults if the cell function is bijective. The authors then present an efficient algorithm to obtain such a test sequence. By extending the concept of C-testability and M-testability to sequential faults, the constant-length test sequence can be obtained. A pipelined array multiplier is ... View full abstract»

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  • A state assignment approach to asynchronous CMOS circuit design

    Publication Year: 1994, Page(s):460 - 469
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    Present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due t... View full abstract»

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  • Uniform parity group distribution in disk arrays with multiple failures

    Publication Year: 1994, Page(s):501 - 506
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    Several new disk arrays have recently been proposed in which the parity groupings are uniformly distributed throughout the array so that the extra workload created by a disk failure can be evenly shared by all the surviving disks, resulting in the best possible degraded mode performance. Many arrays now also put in multiple spare disks so that expensive service calls can be deferred. Furthermore, ... View full abstract»

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  • An analysis of edge fault tolerance in recursively decomposable regular networks

    Publication Year: 1994, Page(s):470 - 475
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Fault tolerance of interconnection networks is one of the major considerations in evaluating the reliability of large scale multiprocessor systems. In the paper, the reliability of a family of regular networks with respect to edge failures is investigated using four different fault tolerance measures. Two probabilistic measures, resilience and restricted resilience, are developed, used to evaluate... View full abstract»

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  • Innovative structures for CMOS combinational gates synthesis

    Publication Year: 1994, Page(s):385 - 399
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1304 KB)

    Design of multiple outputs CMOS combinational gates is studied. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named Delta and Lambda networks. The two techniques can be combined together to obtain further area reductions. Different synthesis algorithms are discussed,... View full abstract»

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  • Concurrent process monitoring with no reference signatures

    Publication Year: 1994, Page(s):475 - 480
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    A simple, inexpensive and time/space efficient signature technique for process monitoring is presented. In this technique, a known signature function is applied to the instruction stream at compilation phase and when the accumulated signature forms an m-out-of-n code, the corresponding instructions are tagged. Error checking is done at run-time by monitoring the signatures accumulated at the tagge... View full abstract»

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  • Reliable floating-point arithmetic algorithms for error-coded operands

    Publication Year: 1994, Page(s):400 - 412
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB)

    Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. The author presents a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respec... View full abstract»

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  • An optimal channel access protocol with multiple reception capacity

    Publication Year: 1994, Page(s):480 - 484
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    A multiple access packet communication model is analyzed in which the users can receive packets on more than one common channel. For this type of system, a new channel access protocol is presented. The authors prove that under heavy homogeneous load the protocol guarantees the maximum achievable throughput among all possible protocols. The general model can be applied to different systems, accordi... View full abstract»

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  • Analysis of asynchronous binary arbitration on digital transmission-line busses

    Publication Year: 1994, Page(s):484 - 489
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    A common misconception is that asynchronous binary arbitration settles in at most four units of bus-propagation delay, irrelevant of the number of arbitration bus lines. The author disproves this conjecture by presenting an arrangement of modules on m bus lines, for which binary arbitration requires [m/2] units of bus-propagation delay to settle. He also proves that for any arrangement of modules ... View full abstract»

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  • A totally self-checking checker for a parallel unordered coding scheme

    Publication Year: 1994, Page(s):490 - 495
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    Bose has developed a parallel unordered coding scheme using only r checkbits for 2r information bits. This code can detect all unidirectional errors and requires simple parallel encoding/decoding. The information symbols can be separated from the check symbols. However, the information symbols containing all zeros and all ones need to be transformed to two other information symbols. Thi... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org