# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 23 of 23
• ### Table of Contents

Publication Year: 2014, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2014, Page(s): C2
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• ### Reducing Complexity and Power of Digital Multibit Error–Feedback $DeltaSigma$ Modulators

Publication Year: 2014, Page(s):641 - 645
| |PDF (691 KB) | HTML

In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element... View full abstract»

• ### A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13- $\mu\hbox{m}$ CMOS Technology

Publication Year: 2014, Page(s):646 - 650
Cited by:  Papers (5)
| |PDF (785 KB) | HTML

A 13.5-mW 10-Gb/s four-level pulse-amplitude modulation (4-PAM) serial link transmitter is presented. To improve the power efficiency, a voltage-mode 4-PAM driver is proposed. It consists of voltage-scaled pull-up and pull-down networks, instead of conventional current switching networks. Not employing a tail current source, the proposed 4-PAM driver achieves the higher output voltage swing and lo... View full abstract»

• ### Fast-Settling Feedforward Automatic Gain Control Based on a New Gain Control Approach

Publication Year: 2014, Page(s):651 - 655
Cited by:  Papers (2)
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This brief presents a feedforward automatic gain control (AGC) circuit with a short settling time. The proposed AGC combines a digital coarse gain setting and an analog fine gain setting, in which the fine gain setting is carried out by a one-step algorithm, which shortens the settling time drastically. The chip is fabricated in 0.13-μm CMOS technology and the measurement results show that ... View full abstract»

• ### An Area-Efficient 96.5%-Peak-Efficiency Cross-Coupled Voltage Doubler With Minimum Supply of 0.8 V

Publication Year: 2014, Page(s):656 - 660
Cited by:  Papers (4)
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An area-efficient cross-coupled voltage doubler (CCVD) with no reversion loss using first-level gate-control mechanism is presented. The proposed design does not require area-consuming resistors or extra power MOSFETs to prevent reversion currents. Through the first-level gate controls, the proposed CCVD is able to use internal nodes to drive the gates of the power MOSFETs without extra buffers, t... View full abstract»

• ### Nanopower CMOS Relaxation Oscillators With Sub-100 $hbox{ppm}/^{circ}hbox{C}$ Temperature Coefficient

Publication Year: 2014, Page(s):661 - 665
Cited by:  Papers (4)
| |PDF (819 KB) | HTML

A low temperature coefficient (TC) current reference and a curvature current source are realized by transistors with different gate-oxide thicknesses. These two current sources are used to realize oscillators with low TCs. These two oscillators of 1.4 MHz and 28 kHz, respectively, are fabricated in the 0.18-μm CMOS process, and their areas are 0.072 and 0.16 mm2, respectively. For the 1.4-M... View full abstract»

• ### Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs

Publication Year: 2014, Page(s):666 - 670
Cited by:  Papers (9)
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This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successive-approximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. I... View full abstract»

• ### Optimizing the Identification of Digital Predistorters for Improved Power Amplifier Linearization Performance

Publication Year: 2014, Page(s):671 - 675
Cited by:  Papers (5)
| |PDF (1293 KB) | HTML

Digital predistortion (DPD) is a cost-effective method to linearize power amplifiers (PAs) in modern wireless transceivers. In block-based predistortion, which is a two-step process involving DPD identification and linearization, the linearization performance is related to the PA output power during identification. In this brief, we investigate this relation and find the optimum PA output power in... View full abstract»

• ### Transformer-Based Current-Reuse Armstrong and Armstrong–Colpitts VCOs

Publication Year: 2014, Page(s):676 - 680
Cited by:  Papers (4)
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This brief proposes two new types of current-reuse voltage-controlled oscillators (VCOs). One is a current-reuse Armstrong VCO (CR-AVCO) and the other is a complementary current-reuse Armstrong-Colpitts VCO (CR-ACVCO). Two one-transistor-based NMOS and PMOS AVCOs are combined into a complementary current-reuse form by sharing a transformer. The CR-ACVCO further improves the CR-AVCO by adding the C... View full abstract»

• ### Simplified Analysis and Simulation of the STF, NTF, and Noise in Continuous-Time $\Delta\Sigma$ Modulators

Publication Year: 2014, Page(s):681 - 685
Cited by:  Papers (2)
| |PDF (1090 KB) | HTML

Determining the signal transfer function (STF), noise transfer function, and in-band thermal noise spectral density of a continuous-time delta-sigma modulator (CTDSM) is challenging due to the periodically time-varying nature of the system. This is particularly so when the loop filter is also time-varying, like in the case of a modulator using a switched-capacitor (SC) feedback digital-to-analog c... View full abstract»

• ### Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs

Publication Year: 2014, Page(s):686 - 690
Cited by:  Papers (7)
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We consider a linear periodically time-varying (LPTV) network (varying with frequency fs) excited by an input x(t). We show (using frequency-domain arguments) that if its output is sampled at fs, one can find a linear time-invariant (LTI) filter, which, when excited by x(t) and output sampled at fs, yields the same sequence as the LPTV network. We then use Tellegen... View full abstract»

• ### A Novel Sourceline Voltage Compensation Circuit and a Wordline Voltage-Generating System for Embedded nor Flash Memory

Publication Year: 2014, Page(s):691 - 695
Cited by:  Papers (1)
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Key blocks used for embedded NOR Flash memory are introduced in this brief, including a novel sourceline (SL) voltage compensation circuit and a wordline (WL) voltage-generating system. The SL voltage compensation circuit controls the output voltage of the charge pump according to the number of cells to be programmed with data “0” to compensate the IR drop on the SL decoding path. Th... View full abstract»

• ### A Low-Power Low-Cost GFSK Demodulator With a Robust Frequency Offset Tolerance

Publication Year: 2014, Page(s):696 - 700
Cited by:  Papers (4)
| |PDF (1059 KB) | HTML

A low-power low-cost Gaussian frequency shift keying demodulator with a robust frequency offset tolerance is presented. A novel automatic pulse duration calibration is employed to keep the pulse durations of the zero-crossing detection output constant against process variation. Additionally, a discrete-time differentiator is adopted to eliminate the negative effect of frequency offset and drift. T... View full abstract»

• ### Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration

Publication Year: 2014, Page(s):701 - 705
Cited by:  Papers (1)
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A new design methodology is proposed for an ultralow in-band phase noise injection-locked frequency multiplier (ILFM) based on open-loop frequency calibration. The prototype ILFM was designed and fabricated in the 65-nm CMOS process. Using an open-loop calibrator without a real-time monitoring loop, the ILFM achieved excellent in-band phase noise with low power consumption and a small silicon area... View full abstract»

• ### A 3-Gb/s/ch Simultaneous Bidirectional Capacitive Coupling Transceiver for 3DICs

Publication Year: 2014, Page(s):706 - 710
Cited by:  Papers (3)
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This brief presents a simultaneous bidirectional capacitive coupling transceiver for intertier communication in 3-D integrated circuits. A novel capacitive coupling interconnect structure is proposed. Optimization of the proposed interconnect structure for minimizing parasitic capacitance achieves the voltage swing VSW of 200 mV at the voltage sensing nodes. The data rate of 3 Gb/s/ch is demonstra... View full abstract»

• ### $(M,p,k)$-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function

Publication Year: 2014, Page(s):711 - 715
Cited by:  Papers (5)
| |PDF (539 KB) | HTML

Linear (order-1) function evaluation schemes, such as bipartite and multipartite tables, are usually effective for low-precision approximations. For high-output precision, the lookup table size is often too large for practical use. This brief investigates the so-called (M,p,k) scheme that reduces the range of an input argument to a very small interval so that trigonometric functions can be approxi... View full abstract»

• ### Stability Preserving Model Reduction Technique and Error Bounds Using Frequency-Limited Gramians for Discrete-Time Systems

Publication Year: 2014, Page(s):716 - 720
Cited by:  Papers (6)
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A frequency-limited interval Gramians-based balanced model reduction technique for discrete-time systems is proposed. The technique provides stable models and also yields frequency-response error bounds. Numerical examples are also presented. The results are comparable with other existing frequency-limited interval Gramians-based model reduction techniques. View full abstract»

• ### Stability Analysis of Linear Time-Invariant Fractional Exponential Delay Systems

Publication Year: 2014, Page(s):721 - 725
Cited by:  Papers (6)
| |PDF (602 KB) | HTML

This brief presents a new approach for the stability analysis of linear fractional exponential delay systems with commensurate orders and multiple commensurate delays that enable us to decide on some cases that were previously open problems. In the proposed approach, first an auxiliary polynomial is generated by mapping the principal sheet of the Riemann surface and a pseudodelay transformation. N... View full abstract»

• ### System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near- $V_{t}$ Computing

Publication Year: 2014, Page(s):726 - 730
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This brief proposes to jointly optimize a switched capacitor voltage regulator module (SC-VRM) combined with a compute core to minimize system energy per instruction. Past work seeking to optimize system energy efficiency has focused on separately maximizing SC-VRM efficiency or operating the compute core at its minimum energy operating point (MEOP). We first propose and verify a core-aware SC-VRM... View full abstract»

• ### Open Access

Publication Year: 2014, Page(s): 731
| |PDF (1156 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2014, Page(s): 732
| |PDF (108 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2014, Page(s): C3
| |PDF (119 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org