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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 25

Publication Year: 2014, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2014, Page(s): C2
| PDF (137 KB)
• ### Self-Consistency and Consistency-Based Detection and Diagnosis of Malicious Circuitry

Publication Year: 2014, Page(s):1845 - 1853
Cited by:  Papers (5)
| | PDF (811 KB) | HTML

Hardware Trojans (HTs) have become a major concern in the modern integrated circuit (IC) industry, especially with the fast growth in IC outsourcing. HT detection and diagnosis are challenging due to the huge number of gates in modern IC designs and the high cost of testing. We propose a scalable and efficient HT detection and diagnosis scheme based on segmentation and consistency analysis of gate... View full abstract»

• ### The Impact of Aging on a Physical Unclonable Function

Publication Year: 2014, Page(s):1854 - 1864
Cited by:  Papers (19)  |  Patents (2)
| | PDF (2706 KB) | HTML

On-chip physical unclonable functions (PUFs) have shown promises to solve several security problems. A PUF's behavior needs to be robust against reversible as well as irreversible temporal variabilities in circuits so that noise in the PUF output is minimized. While the effect of the reversible temporal variabilities on PUFs is well studied, sufficient attention has not been given so far to analyz... View full abstract»

• ### New Implementations of the WG Stream Cipher

Publication Year: 2014, Page(s):1865 - 1878
Cited by:  Papers (3)
| | PDF (2053 KB) | HTML

This paper presents two new hardware designs of the Welch-Gong (WG)-128 cipher, one for the multiple output WG (MOWG) version, and the other for the single output version WG based on type-II optimal normal basis representation. The proposed MOWG design uses signal reuse techniques to reduce hardware cost in the MOWG transformation, whereas it increases the speed by eliminating the inverters from t... View full abstract»

• ### VLSI Design of a Large-Number Multiplier for Fully Homomorphic Encryption

Publication Year: 2014, Page(s):1879 - 1887
Cited by:  Papers (5)
| | PDF (1685 KB) | HTML

This paper presents the design of a power- and area-efficient high-speed 768000-bit multiplier, based on fast Fourier transform multiplication for fully homomorphic encryption operations. A memory-based in-place architecture is presented for the FFT processor that performs 64000-point finite-field FFT operations using a radix-16 computing unit and 16 dual-port SRAMs. By adopting a special prime as... View full abstract»

• ### Optimal and Efficient Algorithms for Multidomain Clock Skew Scheduling

Publication Year: 2014, Page(s):1888 - 1897
| | PDF (2607 KB) | HTML

Clock skew scheduling is an effective technique to improve the performance of sequential circuits. However, with process variations, it becomes more difficult to implement a large number of clock delays in a precise manner. Multidomain clock skew scheduling (MDCSS) is one way to overcome this limitation. In this paper, we prove the NP-completeness of multidomain clock scheduling problem and design... View full abstract»

• ### Active Mode Subclock Power Gating

Publication Year: 2014, Page(s):1898 - 1908
Cited by:  Papers (6)
| | PDF (2134 KB) | HTML

This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (subclock) and 2) reducing the virtual supply to less than Vth rather than shutting down completel... View full abstract»

• ### Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices

Publication Year: 2014, Page(s):1909 - 1919
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Superlattice thin-film thermoelectric coolers (TECs) are emerging as a promising technology for hot spot mitigation in microprocessors. This paper studies the prospect of on-demand cooling with advanced TECs integrated at the back of the heat spreader inside a package (integrated TEC). Using thermal compact models of the chip and package with integrated TECs, the control principles for TEC-assiste... View full abstract»

• ### Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC

Publication Year: 2014, Page(s):1920 - 1933
Cited by:  Papers (5)
| | PDF (1815 KB) | HTML

In 3-D integrated circuits, accurate runtime sensing of on-chip temperature is required to establish dynamic thermal management instruction sets. Placement restrictions and excessive runtime thermal variations, however, compromise the performance and reliability of the sensor readings. Within this framework, a novel methodology for thermal estimation based on unscented Kalman filter, augmented onl... View full abstract»

• ### Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters

Publication Year: 2014, Page(s):1934 - 1944
Cited by:  Papers (2)
| | PDF (3400 KB) | HTML

This paper presents a calibration technique for mismatch-constrained digital-to-analog converters (DACs). The architecture is based on a fully flexible unit current cell assignment. The calibration is performed in a highly digital manner and does not require adjustment of on-chip analog voltages. The method significantly improves low-frequency linearity of the DAC with low hardware overhead and is... View full abstract»

• ### High-Level Modeling of Analog Computational Elements for Signal Processing Applications

Publication Year: 2014, Page(s):1945 - 1953
Cited by:  Papers (10)
| | PDF (1739 KB) | HTML

Large-scale field-programmable analog array ICs have made analog and analog-digital signal processing techniques accessible to a much wider community. Given this opportunity, we present a framework for considering analog signal processing (ASP) techniques for low-power systems. The core of this paper is the definition of an analog abstraction methodology and the creation of a library of high-level... View full abstract»

• ### Distributed On-Chip Switched-Capacitor DC–DC Converters Supporting DVFS in Multicore Systems

Publication Year: 2014, Page(s):1954 - 1967
Cited by:  Papers (4)
| | PDF (2861 KB) | HTML

Dynamic voltage and frequency scaling (DVFS) is a powerful technique to reduce power consumption in a chip multiprocessor. To support DVFS in the multicore power delivery network, we integrate on-chip switched-capacitor (SC) dc-dc converters that can work with multiple conversion ratios to provide varying levels of Vdd supplies. We study the application of such SC converters in multicore chips by ... View full abstract»

• ### Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing

Publication Year: 2014, Page(s):1968 - 1979
Cited by:  Papers (3)
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We propose a compact test generation method for transition faults based on a conflict avoidance driven scheme. A new measure is proposed to estimate the influence inputs, which is the subset of inputs to be specified, needed for detecting transition faults. The value requirements at the pseudoprimary inputs (PPIs) of the second frame of the automatic test pattern generation circuit model are parti... View full abstract»

• ### Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk

Publication Year: 2014, Page(s):1980 - 1989
Cited by:  Papers (2)
| | PDF (2191 KB) | HTML

This paper presents a representative random walk technique for fast transient IR-drop analysis. It selects only a small number of nodes to model the original network for simulation so that the memory and runtime are significantly reduced. Experimental results on benchmark circuits show that our proposed technique can be up to 330 times faster than a commercial simulator while the average error is ... View full abstract»

• ### Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators

Publication Year: 2014, Page(s):1990 - 2003
Cited by:  Papers (3)  |  Patents (1)
| | PDF (3807 KB) | HTML

The computing demand of many signal processing algorithms is dramatically growing because of the increasing complexity of embedded software applications. Concurrently, as process technology scales, the design effort for realizing very large scale integrated circuits and the associated costs are becoming critically high. A possible solution to address this performance/costs challenge is given by cu... View full abstract»

• ### Scalable Effort Hardware Design

Publication Year: 2014, Page(s):2004 - 2016
Cited by:  Papers (7)
| | PDF (2887 KB) | HTML

Applications from several application domains exhibit the property of inherent application resilience, offering entirely new avenues for performance and power optimization by relaxing the conventional requirement of exact (numerical or Boolean) equivalence between the specification and hardware implementation. We propose scalable effort hardware as a design approach to tap the reservoir of applica... View full abstract»

• ### Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability

Publication Year: 2014, Page(s):2017 - 2024
| | PDF (926 KB) | HTML

One way to organize 3-D memories is cell arrays stacked on logic where the upper die layers contain the cell arrays and the bottom layer implements the peripheral logic. A new degree of freedom exists when constructing 3-D memories, which is that the order of the die in the stack can be selected. This paper proposes a new idea that exploits this additional degree of freedom to reduce the cost of y... View full abstract»

• ### Characterization of the Proximity Effect From Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs

Publication Year: 2014, Page(s):2025 - 2029
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The proximity effect of tungsten-filled through-silicon-vias (TSVs) on the threshold voltage and mobility of CMOS devices due to mismatch in thermal expansion coefficients is modeled and verified with measurements. Test structures fabricated in a two-layer 130-nm CMOS 3-D integrated circuit process are measured and compared with 3-D finite element method simulations. Results show that the threshol... View full abstract»

• ### Constructions of Memoryless Crosstalk Avoidance Codes Via ${mathcal{ C}}$ -Transform

Publication Year: 2014, Page(s):2030 - 2033
Cited by:  Papers (4)
| | PDF (315 KB) | HTML

One of the main problems in deep submicrometer designs of high speed buses is the propagation delay due to the crosstalk effect. To alleviate the crosstalk effect, there are several types of crosstalk avoidance codes proposed in the literature. In this paper, we develop explicit constructions of two types of memoryless crosstalk avoidance codes: 1) forbidden overlap codes (FOCs) and 2) forbidden t... View full abstract»

• ### NBTI and Leakage Reduction Using ILP-Based Approach

Publication Year: 2014, Page(s):2034 - 2038
Cited by:  Papers (1)
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We propose an integer linear programming-based formulation to improve the effectiveness of the transmission gate-based technique intended to reduce negative-bias temperature instability and leakage power consumption. We also propose a virtual input pin technique to improve leakage reduction and use path sensitization to reduce area overhead. Simulation results show that combining these techniques ... View full abstract»

• ### Search for Editor-In-Chief of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Publication Year: 2014, Page(s): 2039
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

Publication Year: 2014, Page(s): 2040
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2014, Page(s): C3
| PDF (94 KB)
• ### Search for Editor-In-Chief of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems: Call for applications and nominations

Publication Year: 2014, Page(s): 1
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu