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# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 59

Publication Year: 2014, Page(s):C1 - 3022
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2014, Page(s): C2
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• ### Modeling of Drain Electric Flux Passing Through the BOX Layer in SoI MOSFETs—Part I: Preparation for Modeling Based on Conformal Mapping

Publication Year: 2014, Page(s):3023 - 3029
Cited by:  Papers (2)
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Silicon-on-insulator (SoI) technology has been reported as a technique to improve electrical characteristics over those of bulk MOSFETs. However, this approach results in the disadvantage of increased drain-induced barrier lowering (DIBL) due to drain electric flux (or field) passing through the buried oxide (BOX) layer. Against such a background, the development of a method to easily estimate the... View full abstract»

• ### Modeling of Drain Electric Flux Passing Through the BOX Layer in SoI MOSFETs—Part II: Model Derivation and Validity Confirmation

Publication Year: 2014, Page(s):3030 - 3035
Cited by:  Papers (2)
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Increased drain-induced barrier lowering caused by drain electric flux (or field) passing through the buried-oxide (BOX) layer in silicon-on-insulator (SoI) MOSFETs has been reported as an inherent disadvantage of SoI technology. Part I of this paper discussed derivation of the relationships between coordinates in MOSFETs and potential/stream function in preparation for the modeling of electric fl... View full abstract»

• ### A Compact Explicit Model for Long-Channel Gate-All-Around Junctionless MOSFETs. Part I: DC Characteristics

Publication Year: 2014, Page(s):3036 - 3041
Cited by:  Papers (6)
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In this paper, we solved Poisson equation in cylindrical coordinates using approximations to obtain a compact model for the drain current of long-channel junctionless gate-all-around MOSFETs. The resulting model is analytical, explicit, and valid for depletion and accumulation, and consists of simple physically based equations, for better understanding of this device, and also easier implementatio... View full abstract»

• ### A Compact Explicit Model for Long-Channel Gate-All-Around Junctionless MOSFETs. Part II: Total Charges and Intrinsic Capacitance Characteristics

Publication Year: 2014, Page(s):3042 - 3046
Cited by:  Papers (6)
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Analytical and explicit expressions are derived for intrinsic capacitances of the junctionless gate-all-around transistor, from the charge-control model, valid in the two regions of operation, depletion mode and accumulation mode. The advantage of this model is that it reduces to simple expressions for each region, giving a higher computation speed. We obtain very good agreement between the calcul... View full abstract»

• ### Thermoreflectance CCD Imaging of Self-Heating in Power MOSFET Arrays

Publication Year: 2014, Page(s):3047 - 3053
Cited by:  Papers (2)
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Thermoreflectance imaging with high spatial resolution is used to inspect self-heating distribution in active high power (4A) metal-oxide-semiconductor field-effect transistor transistor arrays designed for high-frequency (MHz) operation. Peak temperature change and self-heating distribution is analyzed for both low- and high-dc bias cases and for different ambient die temperatures (296-373 K). Th... View full abstract»

• ### 2-D Analytical Model for the Threshold Voltage of a Tunneling FET With Localized Charges

Publication Year: 2014, Page(s):3054 - 3059
Cited by:  Papers (13)
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In this paper, we have developed a 2-D analytical model for the surface potential and threshold voltage of a tunneling field-effect transistor (TFET) with localized charges in the oxide. These charges are generated in the oxide due to hot carrier effects in the channel. The models are derived by dividing the channel into damaged and undamaged regions and then solving the 2-D Poisson's equation in ... View full abstract»

• ### Germanium n+/p Shallow Junction With Record Rectification Ratio Formed by Low-Temperature Preannealing and Excimer Laser Annealing

Publication Year: 2014, Page(s):3060 - 3065
Cited by:  Papers (9)
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A germanium n+/p shallow junction formed by a combination of low-temperature preannealing (LTPA) and excimer laser annealing at a low fluence of 150 mJ/cm2 for phosphorus-implanted germanium is demonstrated. The LTPA step plays a critical role in annihilating the implantation damages and significantly suppressing phosphorus diffusion during laser annealing process, resulting ... View full abstract»

• ### CMOS Logic Device and Circuit Performance of Si Gate All Around Nanowire MOSFET

Publication Year: 2014, Page(s):3066 - 3074
Cited by:  Papers (11)
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In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWF... View full abstract»

• ### Enhanced Performance of Single Poly-Silicon EEPROM Cell With a Tungsten Finger Coupling Structure by Full CMOS Process

Publication Year: 2014, Page(s):3075 - 3080
Cited by:  Papers (3)
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A single poly-silicon electrically erasable programmable read only memory cell with a tungsten finger coupling structure by fully compatible 0.13-μm CMOS process is proposed for the first time in this paper and its performances are compared with the conventional poly-silicon finger coupling cell. Results show that the tungsten finger coupling cell has smaller drain-induced barrier lowering ... View full abstract»

• ### Development of a Technique for Characterizing Bias Temperature Instability-Induced Device-to-Device Variation at SRAM-Relevant Conditions

Publication Year: 2014, Page(s):3081 - 3089
Cited by:  Papers (6)
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SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse-$$I$$ -$$V$$ , rand... View full abstract»

• ### A Study of Overlaying Dielectric Layer and Its Local Geometry Effects on TSV-Induced KOZ in 3-D IC

Publication Year: 2014, Page(s):3090 - 3095
Cited by:  Papers (5)
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The aim of this paper is to investigate the effects of overlaying dielectric layer and its local geometry on keep-out zone (KOZ) induced from through-silicon via (TSV) in 3-D integrated circuit applications. Prior to the study, the saturated current changes (or corresponding carrier mobility changes) of both nMOS and pMOS transistors from the finite element simulations are validated with experimen... View full abstract»

• ### Quantum Modeling of the Carrier Mobility in FDSOI Devices

Publication Year: 2014, Page(s):3096 - 3102
Cited by:  Papers (9)
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We compute the electron and hole mobilities in ultrathin body and buried oxide, fully depleted silicon on insulator devices with various high-$$\kappa$$ metal gate-stacks using nonequilibrium Green's functions (NEGF). We compare our results with experimental data at different back gate biases and temperatures. That way, we are able to deembed the different contributions to the carrier mobility in... View full abstract»

• ### Predictive Hot-Carrier Modeling of n-Channel MOSFETs

Publication Year: 2014, Page(s):3103 - 3110
Cited by:  Papers (22)
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We present a physics-based hot-carrier degradation (HCD) model and validate it against measurement data on SiON n-channel MOSFETs of various channel lengths, from ultrascaled to long-channel transistors. The HCD model is capable of representing HCD in all these transistors stressed under different conditions using a unique set of model parameters. The degradation is modeled as a dissociation of Si... View full abstract»

• ### Extraction of Gate Resistance in Sub-100-nm MOSFETs With Statistical Verification

Publication Year: 2014, Page(s):3111 - 3117
Cited by:  Papers (1)
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This paper presents an improved z-parameter based approach to extract the gate resistance at low frequencies. The effectiveness of this approach, compared with other y-parameter based approaches, is verified using 430 samples fabricated in 40-, 55-, 90-, and 110-nm CMOS technology nodes. The influence of the nonquasi-static (NQS) effect, resulting from the distributed channel resistance, on the ga... View full abstract»

• ### A Conductive AFM Nanoscale Analysis of NBTI and Channel Hot-Carrier Degradation in MOSFETs

Publication Year: 2014, Page(s):3118 - 3124
Cited by:  Papers (1)
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This paper addresses the impact of different electrical stresses on nanoscale electrical properties of the MOSFET gate dielectric. Using a conductive atomic force microscope (CAFM) for the first time, the gate oxide has been analyzed after bias temperature instability (BTI) and channel hot-carrier (CHC) stresses. The CAFM explicitly shows that while the degradation induced along the channel by a n... View full abstract»

• ### Performance of a-SiGe:H Thin-Film Solar Cells on High-Heat Dissipation Flexible Ceramic Printable Circuit Board

Publication Year: 2014, Page(s):3125 - 3130
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In this paper, a flexible ceramic printable circuit board (FCPCB) consisting aluminum (Al) metal layer and ceramic layer is used as a substrate for solar cell fabrication. A 3-layer graded bandgap hydrogenated amorphous silicon-germanium absorber and an etched Al-doped zinc oxide are applied to single-junction cell fabrication to increase the cell conversion efficiency up to 6.3%. For temperature ... View full abstract»

• ### Implementation of DPL-DD Model for the Simulation of Nanoscale MOS Devices

Publication Year: 2014, Page(s):3131 - 3138
Cited by:  Papers (5)
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This paper investigates electrothermal aspects of high-k material as well as silicon-on-insulator (SoI) technology in the nanoscale nMOSFET by the numerical simulation of dual-phase-lag (DPL) heat conduction model under the effect of self-heating phenomenon. Three types of MOS devices including bulk, SoI, and high-k MOSFETs are considered. All of the electrothermal parameters are considered temper... View full abstract»

• ### Fast Ramped Voltage Characterization of Single Trap Bias and Temperature Impact on Time-Dependent $V_{\rm TH}$ Variability

Publication Year: 2014, Page(s):3139 - 3144
Cited by:  Papers (6)
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Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable VTH shifts and fluctuations, which are even visible during the ID-VG tracing in nanometer-scaled devices. Exploiting this feature, we have developed a methodol... View full abstract»

• ### Analysis of Time Dependent Electric Field Degradation in AlGaN/GaN HEMTs

Publication Year: 2014, Page(s):3145 - 3151
Cited by:  Papers (3)
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The authors report on an electrical and optical analysis of AlGaN/GaN HEMTs stressed under high electric field conditions into a state of permanent degradation, evidenced by an increase in OFF-state leakage current and a reduction in breakdown voltage. A method of stress testing AlGaN/GaN HEMTs to voltages close to breakdown while protecting the device from catastrophic failure is presented. Using... View full abstract»

• ### Impact of Isolation-Feature Geometry on Self-Heating of AlGaN/GaN HFETs

Publication Year: 2014, Page(s):3152 - 3158
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Correlation between the isolation-feature geometry and average channel temperature of AlGaN/GaN heterojunction field-effect transistors (HFETs) is investigated. The reported transistors of this paper were realized on a variety of isolation-feature geometries resembling the following structures: 1) island; 2) fin; 3) comb; and 4) ladder. The average channel temperature of the devices from all categ... View full abstract»

• ### Plasma Doping of InGaAs at Elevated Substrate Temperature for Reduced Sheet Resistance and Defect Formation

Publication Year: 2014, Page(s):3159 - 3165
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Plasma doping (PLAD), a high-throughput ion implantation technique capable of achieving ultrashallow junctions and conformal doping of 3-D structures such as fin field-effect transistors, is investigated as an alternative to conventional beam-line ion implantation for InGaAs at advanced technology nodes. The PLAD at an elevated substrate temperature (ET-PLAD) is studied and reported for InGaAs for... View full abstract»

• ### An Analytical Model for the Forming Process of Conductive-Bridge Resistive-Switching Random-Access Memory

Publication Year: 2014, Page(s):3166 - 3171
Cited by:  Papers (4)
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An analytical model for the forming process of conductive-bridge resistive-switching random-access memory is developed. The measurable forming time can be calculated using this model giving the biasing condition and is verified to be correct through comparison with the experimental data. The forming time has been shown to have multiple-slopes in exponential dependence on the applied voltage, in ag... View full abstract»

• ### Multifunction Behavior of a Vertical MOSFET With Trench Body Structure and New Erase Mechanism for Use in 1T-DRAM

Publication Year: 2014, Page(s):3172 - 3178
Cited by:  Papers (1)
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A multifunctional vertical silicon-on-insulator-based metal-oxide-semiconductor (VSoI-MOS) field-effect transistor with trench body structure was designed. It can act as a high-performance transistor (HPT) or a capacitorless one-transistor dynamic random access memory (1T-DRAM), depending on the drain/source location and its electrical and transient performances. The VSoI-MOS operated in HPT mode ... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy