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IEEE Design & Test

Issue 4 • Aug. 2014

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Displaying Results 1 - 25 of 25
  • [Front cover]

    Publication Year: 2014, Page(s): C1
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  • [Front inside cover]

    Publication Year: 2014, Page(s): C2
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  • IEEE Design & Test of Computers publication information

    Publication Year: 2014, Page(s): 1
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  • Table of contents

    Publication Year: 2014, Page(s): 2
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  • Departments

    Publication Year: 2014, Page(s): 3
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  • The Bottom Line of Complex ICs and Systems on Chip [From the EIC]

    Publication Year: 2014, Page(s):4 - 5
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  • Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges

    Publication Year: 2014, Page(s):6 - 15
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB) | HTML iconHTML

    Accurate yield estimation is always an important director of design. For analog/mixed signal circuits, the dominant yield loss mechanisms are parametric in nature. This paper provides an informative discussion of varied approaches to parametric yield estimation, including recently developed methods that provide a highly accurate and fast alternative to Monte Carlo methods for some types of analysi... View full abstract»

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  • On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs

    Publication Year: 2014, Page(s):16 - 26
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1502 KB) | HTML iconHTML

    This article discusses a design-for-test (DFT) architecture for detecting and repairing faulty interconnects in 3-D IC circuits utilizing through silicon via (TSV) and interposer technology. The yield of such circuits depends highly on the ability to have functioning interconnects which connect the various dies. The authors also propose a built-in-self-test (BIST) framework to enable at-speed test... View full abstract»

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  • Real-Time Power Sensors for Intelligent Power Management and Beyond

    Publication Year: 2014, Page(s):27 - 35
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (814 KB) | HTML iconHTML

    This article presents a low-overhead on-chip power sensor design that enables cross-layer power management policy used in future computing systems. View full abstract»

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  • PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning

    Publication Year: 2014, Page(s):36 - 42
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (794 KB) | HTML iconHTML

    A cell-based phase-locked loop (PLL) can be realized automatically by a compiler to support up to 1-GHz on-chip clock signal generation. This latest design technology is poised to have an impact on the future VLSI test technology, e.g., as we will demonstrate in this paper that it is useful in the timing circuit for binning the leakage of a TSV in a 3-D IC. Unlike previous delay-line-based leakage... View full abstract»

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  • Design Considerations for Cooling High Heat Flux IC Chips With Microchannels

    Publication Year: 2014, Page(s):43 - 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (489 KB) | HTML iconHTML

    Thermal emergency in integrated circuits has become an important issue with aggressive scaling trends. Several novel cooling techniques are investigated in both academia and industry. Sophisticated active cooling techniques are required to mitigate the thermal issues faced by the chips in the current and future technologies. View full abstract»

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  • Semantic Technology

    Publication Year: 2014, Page(s): 51
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  • ICCAD Roundtable The Many Challenges of Triple Patterning [ICCAD Roundtable]

    Publication Year: 2014, Page(s):52 - 58
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  • Phaser Data

    Publication Year: 2014, Page(s): 59
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  • Let's Get Physical [review of "Physical Layer Multi-core Prototyping: A Dataflow-based approach for LTE eNodeB"]

    Publication Year: 2014, Page(s):60 - 61
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  • IEEE Was Here

    Publication Year: 2014, Page(s): 62
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  • IEEE Proceedings

    Publication Year: 2014, Page(s): 63
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  • CEDA Currents

    Publication Year: 2014, Page(s):64 - 65
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  • Educational Activities

    Publication Year: 2014, Page(s): 66
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  • myIEEE

    Publication Year: 2014, Page(s): 67
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  • Test Technology TC Newsletter

    Publication Year: 2014, Page(s):68 - 69
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  • Open Access Publishing

    Publication Year: 2014, Page(s): 70
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  • The Obligatory Internet-of-Things Column

    Publication Year: 2014, Page(s):71 - 72
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  • [Back inside cover]

    Publication Year: 2014, Page(s): C3
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  • [Back cover]

    Publication Year: 2014, Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)