# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 23 of 23

Publication Year: 2014, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2014, Page(s): C2
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• ### High-Efficiency Power Amplifier Using an Active Second-Harmonic Injection Technique Under Optimized Third-Harmonic Termination

Publication Year: 2014, Page(s):549 - 553
Cited by:  Papers (7)
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This brief presents an active second-harmonic injection technique to improve the efficiency and bandwidth for high-efficiency power amplifiers (PAs). An optimum third-harmonic termination condition was examined for higher efficiency after the second-harmonic injection using a multiharmonic load-pull simulation. It was determined that the optimum third-harmonic termination is the same as that of th... View full abstract»

• ### A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- $\mu\hbox{m}$ CMOS

Publication Year: 2014, Page(s):554 - 558
Cited by:  Papers (1)
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This brief describes a wide-range operating false-lock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit does not require t... View full abstract»

• ### A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes

Publication Year: 2014, Page(s):559 - 563
Cited by:  Papers (6)
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This study demonstrates a wide frequency tuning range LC voltage-controlled oscillator (LC-VCO) with an active inductor in a 90-nm CMOS process. As the proposed LC-VCO is intended to be extremely flexible without redesign for several new-generation SerDes interfaces, a wide operating frequency makes the phase-locked loop (PLL) applicable to the multistandards. To demonstrate a highly competitive d... View full abstract»

• ### A Low-Power 2.4-GHz Receiver Front End With a Lateral Current-Reusing Technique

Publication Year: 2014, Page(s):564 - 568
Cited by:  Papers (2)
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A 2.4-GHz current-reused receiver front end is presented in this brief. Instead of using the traditional stack-on current-reusing scheme that compresses the voltage headroom, the proposed front end employs a lateral current-shunt branch to share most of the dc bias current of the transconductance transistors in an LNA and a mixer. To prevent the signal interaction between the two modules, an LC ta... View full abstract»

• ### Fixator–Norator Pairs Versus Direct Analytical Tools in Performing Analog Circuit Designs

Publication Year: 2014, Page(s):569 - 573
Cited by:  Papers (4)
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Two analog circuit design approaches are introduced and compared. They are used for partial designs with certain given design criteria. The first approach, which is called direct analytical, works through the circuit conductance matrix, and it needs linearity to perform. The second approach uses fixator-norator pairs (FNPs), changing an analysis into a design problem. The two methods are shown to ... View full abstract»

• ### Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth

Publication Year: 2014, Page(s):574 - 578
Cited by:  Papers (4)
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A CMOS class-AB variable-gain voltage feedback current operational amplifier (VFCOA) is presented. The implementation is based on class-AB second-generation current conveyors and exploits an electronically tunable transistorized feedback network. The circuit combines high linearity, low power consumption, and variable-gain range from 0 to 24 dB with nearly constant bandwidth, tunable from 1 to 3 M... View full abstract»

• ### Quantifying the Complexity of DC–DC Switching Converters by Joint Entropy

Publication Year: 2014, Page(s):579 - 583
Cited by:  Papers (3)
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Joint entropy is used to quantify the complex nonlinear states of dc-dc switching converters in this brief. The switching instant symbolic sequence (SISS) and the topological structural symbolic sequence (TSSS) are presented based on the characteristics of dc-dc converters. Transforming SISS and TSSS into the decimal symbolic sequences, joint entropy is obtained as the index to quantify the nonlin... View full abstract»

• ### A 10-bit 110 kS/s 1.16 $muhbox{W}$ SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications

Publication Year: 2014, Page(s):584 - 588
Cited by:  Papers (6)
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A 10-bit 110-kS/s successive-approximation analog-to-digital converter (ADC) for multichannel biomedical applications is presented. In order to achieve low-power operation, the ADC utilizes a reduced-speed dynamic comparator, a low-complexity calibration technique, a hybrid single/differential digital-to-analog converter architecture, and an attenuation capacitor with low sensitivity to mismatch e... View full abstract»

• ### 7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

Publication Year: 2014, Page(s):589 - 593
Cited by:  Papers (9)
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In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical a... View full abstract»

• ### A Compensation Technique for Two-Stage Differential OTAs

Publication Year: 2014, Page(s):594 - 598
Cited by:  Papers (10)
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In this brief, a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3-dB bandwidth, the unity gain frequency, and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole. The phase margin shows good robustness against pr... View full abstract»

• ### Improvements in Light-Load Efficiency and Operation Frequency for Low-Voltage Current-Mode Integrated Boost Converters

Publication Year: 2014, Page(s):599 - 603
Cited by:  Papers (1)
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This brief presents design techniques to improve both the power efficiency and the operation frequency of low-voltage current-mode boost converters for single-cell NiMH battery applications. For delivering a wide range of load currents, a cross-conduction-free width-switching (CCF-WS) technique is developed to eliminate the short-circuit power loss associated with switching different segments of o... View full abstract»

• ### A 15-V Bidirectional Ultrasound Interface Analog Front-End IC for Medical Imaging Using Standard CMOS Technology

Publication Year: 2014, Page(s):604 - 608
Cited by:  Papers (4)
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A high-voltage (HV) interface analog front-end (AFE) integrated circuit (IC) for medical ultrasound imaging applications using 0.18-μm standard CMOS process is presented. The proposed AFE IC includes a HV pulser in the transmit path that safely generates up to 15-Vpp of unipolar pulses at 2.6 MHz, a HV switch for isolation between transmitter and receiver frontend parts, and a 95.1-dB:... View full abstract»

• ### Hardware Architecture for List Successive Cancellation Decoding of Polar Codes

Publication Year: 2014, Page(s):609 - 613
Cited by:  Papers (32)
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This brief presents a hardware architecture and algorithmic improvements for list successive cancellation (SC) decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a block length of N=1024 bits and list sizes L=2, 4 using a UMC 90 n... View full abstract»

• ### $l_{2}-l_{\infty}$ Suppression of Limit Cycles in Interfered Two-Dimensional Digital Filters: A Fornasini–Marchesini Model Case

Publication Year: 2014, Page(s):614 - 618
Cited by:  Papers (46)
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Recently, Ahn proposed an l2-l∞ stability criterion for interfered two-dimensional (2-D) digital filters described by the Roesser model. However, until now, no criteria for interfered 2-D digital filters in the Fornasini-Marchesini (FM) model have been studied. As a continuation of the results, this brief proposes a new criterion for the l2-l∞ View full abstract»

• ### Finite-Time Containment Control for Second-Order Multiagent Systems Under Directed Topology

Publication Year: 2014, Page(s):619 - 623
Cited by:  Papers (27)
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This brief investigates the finite-time containment control for second-order multiagent systems with multiple dynamic leaders under a fixed directed communication topology. In particular, the studied systems are composed of the multiple dynamic leaders with bounded unknown acceleration inputs and the followers with bounded disturbances. A new continuous nonlinear containment control protocol is co... View full abstract»

• ### Extraction of Poles and Zeros of an $RC$ Circuit With Roots on the Real Axis

Publication Year: 2014, Page(s):624 - 628
Cited by:  Papers (3)
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A graphical/numerical technique is presented for the extraction of roots (poles and zeros) of an RC circuit, where the roots lay on the left-hand side of the real axis (RLHP) in the s-plane. The method constructs a corresponding LC circuit for the RC circuit and, as shown, all the RLHP roots in the RC circuit are shifted to the jω axis, where the swiping-frequency signals exist. It is also ... View full abstract»

• ### A DC–DC Converter for a Fully Integrated PID Compensator With a Single Capacitor

Publication Year: 2014, Page(s):629 - 633
Cited by:  Papers (6)
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In this brief, proportional-integral-derivative (PID) compensation with a single capacitor for a fully integrated controller employed in a direct DC-DC converter operating in a voltage mode is presented. To make up a compact-area on-chip controller, a novel compensator is proposed, utilizing the AC ripple current of the inductor, which enables the PID controller to be implemented with only one cap... View full abstract»

• ### A 0.42-V Input Boost dc–dc Converter With Pseudo-Digital Pulsewidth Modulation

Publication Year: 2014, Page(s):634 - 638
Cited by:  Papers (1)
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A pseudo-digital pulsewidth modulation (P-DPWM) controlled boost direct current-direct current converter is presented in this brief. By applying low-voltage analog design techniques into the traditional digital pulsewidth modulation (DPWM) structure, the proposed P-DPWM achieves new features of high resolution, low power, and small area while retaining the low-supply feature of the DPWM. A test ch... View full abstract»

• ### Corrections to “Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference” [Jun 12 331-335]

Publication Year: 2014, Page(s): 639
Cited by:  Papers (1)
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In the above-named article [ibid., vol. 59, no. 6, pp. 331-335, Jun. 2012], two equations were omitted, and one equation was misplaced during proofing. The correct equations for the second paragraph of Section I (page 331) and in the first paragraph of Section II (page 332) are provided. It is then shown that, with this loop filter, the 3-dB frequency and damping factor for the phase-locked loop a... View full abstract»

• ### IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2014, Page(s): 640
| |PDF (108 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2014, Page(s): C3
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## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org