# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 68

Publication Year: 2014, Page(s):C1 - 2611
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2014, Page(s): C2
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• ### An Improved Transfer Current Model for RF and mm-Wave SiGe(C) Heterojunction Bipolar Transistors

Publication Year: 2014, Page(s):2612 - 2618
Cited by:  Papers (11)
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The carrier transport in advanced SiGe heterojunction bipolar transistor (HBT) process technologies exhibits bandgap-related transport effects that not only impact the transconductance and output conductance characteristics, but are also difficult to describe accurately by compact models. This paper addresses the modeling of bandgap-related effects in the collector current by formulating an improv... View full abstract»

• ### A Correlation Between Oxygen Vacancies and Reliability Characteristics in a Single Zirconium Oxide Metal-Insulator-Metal Capacitor

Publication Year: 2014, Page(s):2619 - 2627
Cited by:  Papers (2)
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A correlation between reliability characteristics and failure mechanisms for time-dependent dielectric breakdown for a single ZrO2 metal-insulator-metal capacitor has been studied. Frenkel-Poole emission was the dominant mechanism in the high electric field region. The extracted dynamic constant and trap energy level were 4.013 and 0.963 eV, respectively. The variation of α as a ... View full abstract»

• ### Carbon Nanotube Nonvolatile Thin-Film Transistors With (Bi,Nd)4Ti3O12 Gate Insulators

Publication Year: 2014, Page(s):2628 - 2632
Cited by:  Papers (1)
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Single-walled carbon nanotube (SWCNT) nonvolatile thin-film transistors (TFTs) with (Bi,Nd)4Ti3O12 (BNT) gate insulators were fabricated. The electrical properties of BNT films and SWCNT/BNT TFTs were investigated. The subthreshold swing, the threshold voltage, the channel mobility, and the ON/OFF ratio of SWCNT/BNT TFTs reach to 62.5 mV/decade, 0.45 V, 1.3 ×... View full abstract»

• ### Accurate Prediction of Device Performance Based on 2-D Carrier Profiles in the Presence of Extensive Mobile Carrier Diffusion

Publication Year: 2014, Page(s):2633 - 2639
Cited by:  Papers (2)
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In this paper, we illustrate how high-resolution 2-D carrier profiles from scanning spreading resistance microscopy (SSRM) can be used to predict and understand device performance of dynamic random access memory peripheral transistors with high-k metal gate and ultrashallow junctions. In an earlier study on high-speed complementary metal-oxide-semiconductor logic, the 2-D carrier profiles from SSR... View full abstract»

• ### Modeling the Channel Charge and Potential in Quasi-Ballistic Nanoscale Double-Gate MOSFETs

Publication Year: 2014, Page(s):2640 - 2646
Cited by:  Papers (7)
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In this paper, we present an analytical semiempirical model of the profile of the channel charge and potential in quasi-ballistic double-gate (DG) MOSFETs. The charge model is based on the premise of separating the charge density in the quasi-ballistic channel into two hypothetical components: 1) exclusively ballistic (collision-free) and 2) collision-dominated components, which are governed by th... View full abstract»

• ### GeTe Liner Stressor Featuring Phase-Change- Induced Volume Contraction for Strain Engineering of Sub-50-nm p-Channel FinFETs: Simulation and Electrical Characterization

Publication Year: 2014, Page(s):2647 - 2655
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We report the experimental demonstration of strained p-channel FinFETs featuring a GeTe liner stressor that exhibits very large volume contraction (~10%) during phase change. Conformally grown GeTe liner was formed on FinFETs with sub-50-nm gate length LG. When the GeTe liner changes phase from amorphous (α-GeTe) to polycrystalline (c-GeTe) state, it contracts and imparts very hi... View full abstract»

• ### High-Performance Germanium p- and n-MOSFETs With NiGe Source/Drain

Publication Year: 2014, Page(s):2656 - 2661
Cited by:  Papers (5)
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In this paper, we report Ge pand n-channel metal- oxide-semiconductor field-effect transistors (MOSFETs) with NiGe source/drain (S/D) with high performance and low leakage current. The forward/reverse current ratio of the NiGe/n-Ge and NiGe/p-Ge junctions were ~105 and ~2 × 104 at |V| = ±1 V, respectively. Interface state densities Dit of Al2O3 View full abstract»

• ### An Ultralow EOT Ge MOS Device With Tetragonal HfO2 and High Quality HfxGeyO Interfacial Layer

Publication Year: 2014, Page(s):2662 - 2667
Cited by:  Papers (11)
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A Ge MOS device with an ultralow equivalent oxide thickness of ~0.5 nm and acceptable leakage current of 0.5 A/cm2 is presented in this paper. The superior characteristics can be attributed to a tetragonal HfO2 with a higher k value (k ~ 31) and comparable bandgap. In addition, a Ge MOS device with tetragonal phase HfO2 (t-HfO2) also shows a lower leakag... View full abstract»

• ### A Compact Model of Program Window in HfOx RRAM Devices for Conductive Filament Characteristics Analysis

Publication Year: 2014, Page(s):2668 - 2673
Cited by:  Papers (40)
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This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correla... View full abstract»

• ### Electron-Hole Bilayer TFET: Experiments and Comments

Publication Year: 2014, Page(s):2674 - 2681
Cited by:  Papers (17)
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We investigate Si/Si0.85Ge0.15 fully depleted-SOI tunnel FET (TFET) devices operated in the electron-hole bilayer (EHB) mode. The application of negative bias on front gate and positive bias on back gate results in confined hole and electron layers that are expected to enable vertical band-to-band tunneling (BTBT). The idea of the EHB-TFET device is to enhance the tunneling c... View full abstract»

• ### Understanding and Modeling of Diode Voltage Overshoots During Fast Transient ESD Events

Publication Year: 2014, Page(s):2682 - 2689
Cited by:  Papers (4)
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Diodes in forward direction exhibit excellent ESD ruggedness and are thus widely used in both discrete and on-chip electro-static discharge (ESD) protection devices. Due to the conductivity modulation under an ESD stress, a transient voltage overshoot is observed at the beginning of a fast discharge event. Since the voltage overshoot can be harmful, understanding the origin of the overshoot is cru... View full abstract»

• ### An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs

Publication Year: 2014, Page(s):2690 - 2696
Cited by:  Papers (19)
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In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified. The dual-modulation effects in TFETs that the surface potential of the channel is alternatively controlled by the gate bias and drain bias in different operating regimes are emphasized and studied. The transition point corresponding to the switching betwee... View full abstract»

• ### Quantum Analytical Modeling for Device Parameters and $I$ – $V$ Characteristics of Nanoscale Dual-Material Double-Gate Silicon-on-Nothing MOSFET

Publication Year: 2014, Page(s):2697 - 2704
Cited by:  Papers (4)
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This paper presents the quantum analytical model, based on the self-consistent solution of 1-D Schrödinger equation and 2-D Poisson's equation for the ultrascaled dual-material double-gate (DMDG) silicon-on-nothing MOSFET structure. The quantum mechanical effects (QMEs) have been incorporated in our model to derive the analytical current expressions for the first time ever. Extensive calcu... View full abstract»

• ### Threshold Voltage Variations Due to Oblique Single Grain Boundary in Sub-50-nm Polysilicon Channel

Publication Year: 2014, Page(s):2705 - 2710
Cited by:  Papers (4)
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We investigate the effect of single grain boundary (SGB) with arbitrary angles on the threshold voltage (Vth) variation in sub-50-nm polysilicon (poly-Si) channel devices using 3-D simulation. An SGB in the poly-Si channel causes changes in potential barrier profile resulting in the variation of Vth. As the planar devices scale down to 20-nm, oblique SGB can significantly inc... View full abstract»

• ### Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology

Publication Year: 2014, Page(s):2711 - 2718
Cited by:  Papers (8)
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FinFET technology is prone to suffer from line edge roughness (LER)-based VT variation with scaling. It also lacks a simple implementation of multiple VT technology needed for power management. To address these challenges, in this paper we present an epitaxially defined FinFET (EDFinFET) as an alternate to FinFET architecture for nodes 15 nm and beyond. We show by statistical... View full abstract»

• ### Optimum Bandgap and Supply Voltage in Tunnel FETs

Publication Year: 2014, Page(s):2719 - 2724
Cited by:  Papers (7)
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A physics-based analytic model of the ON- and OFF-currents in a homojunction tunnel field-effect transistor (TFET) is used to understand the relationship between bandgap, gate length, ON-current, OFF-current, ON/OFF current ratio, and supply voltage to meet minimum energy requirements. The model, which applies to direct-bandgap semiconductors, is validated against numerical simulations to show tha... View full abstract»

• ### Dead Time Compensation in CMOS Single Photon Avalanche Diodes With Active Quenching and External Reset

Publication Year: 2014, Page(s):2725 - 2731
Cited by:  Papers (7)
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Single photon avalanche diodes (SPADs) in CMOS are becoming increasingly interesting devices for timing applications, such as fluorescence lifetime imaging, positron emission tomography, and time of flight mass spectroscopy. The CMOS allows integration of functionalities like time-to-digital converters within the same pixel, and the manufacturing of large format arrays. Dead time has to be taken i... View full abstract»

• ### A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry

Publication Year: 2014, Page(s):2732 - 2737
Cited by:  Papers (7)
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Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this paper, we demonstrate that using the unique quasi-linear relationship between the surface potentials, it is possible to develop compact model for CDG-MOSFETs without such approximation while preserving the mathematical complexity at the same level o... View full abstract»

• ### Fin Shape Impact on FinFET Leakage With Application to Multithreshold and Ultralow-Leakage FinFET Design

Publication Year: 2014, Page(s):2738 - 2744
Cited by:  Papers (30)
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FinFETs have emerged as the solution to short channel effects at the 22-nm technology node and beyond. Previously, there have been few studies on the impact of fin cross section shape on transistor leakage. We show for the first time that fin shape significantly impacts transistor leakage in bulk tri-gate nFinFETs with thin fins when the fin body doping profile is optimized to minimize leakage. We... View full abstract»

• ### Problems With the Continuous Doping TCAD Simulations of Decananometer CMOS Transistors

Publication Year: 2014, Page(s):2745 - 2751
Cited by:  Papers (7)
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In this paper, we compare results from atomistic and continuous simulation of decananometer scale CMOS transistors. We study the behavior of important figures of merit, including threshold voltage, subthreshold slope, OFF-current, and ON-current. We provide physical explanation for the origin of the discrepancies between the averaged values obtained from the statistical simulations and the results... View full abstract»

• ### Thermal Modeling of Multi-Fin Field Effect Transistor Structure Using Proper Orthogonal Decomposition

Publication Year: 2014, Page(s):2752 - 2759
Cited by:  Papers (5)
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An approach is proposed to project thermal behavior in a semiconductor integrated-circuit structure onto a functional space based on the proper orthogonal decomposition (POD). The approach substantially reduces the numerical degrees of freedom (DOF) needed for thermal simulations and requires no assumptions about physical geometry, dimensions, or heat flow paths. The POD approach is applied to a m... View full abstract»

• ### Investigation of Temperature-Dependent Characteristics of AlGaN/GaN MOS-HEMT by Using Hydrogen Peroxide Oxidation Technique

Publication Year: 2014, Page(s):2760 - 2766
Cited by:  Papers (11)
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This paper investigates the temperature-dependent performances of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT). The gate dielectric layer and surface passivation layer are formed by the H2O2 oxidation technique. The gate dielectric quality is estimated by the breakdown electric field (EBD) and low-frequency noise. The capacitance-voltage (C... View full abstract»

• ### P2S5/(NH4)2Sx-Based Sulfur Monolayer Doping for Source/Drain Extensions in n-Channel InGaAs FETs

Publication Year: 2014, Page(s):2767 - 2773
Cited by:  Papers (2)
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Ultrashallow junctions that are abrupt and have low resistance are needed for the source/drain extensions (SDEs) of MOSFETs at future technology nodes. In addition, the use of 3-D devices, such as FinFETs or nanowire FETs, will require a doping process that is conformal. In this paper, we discuss P2S5/(NH4)2Sx-based doping for potential use in... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy