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Electron Devices, IEEE Transactions on

Issue 8 • Date Aug. 2014

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Displaying Results 1 - 25 of 68
  • Table of contents

    Publication Year: 2014 , Page(s): C1 - 2611
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  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2014 , Page(s): C2
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  • An Improved Transfer Current Model for RF and mm-Wave SiGe(C) Heterojunction Bipolar Transistors

    Publication Year: 2014 , Page(s): 2612 - 2618
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1100 KB) |  | HTML iconHTML  

    The carrier transport in advanced SiGe heterojunction bipolar transistor (HBT) process technologies exhibits bandgap-related transport effects that not only impact the transconductance and output conductance characteristics, but are also difficult to describe accurately by compact models. This paper addresses the modeling of bandgap-related effects in the collector current by formulating an improved version of a generalized integral charge-control relation (GICCR). As a result, the experimentally observed degradation of the transconductance at low and medium current injection, which is a strong function of the Ge grading, as well as the output conductance are described by simple bias- and temperature-dependent formulations of the GICCR weight factors. The derived formulations fit seamlessly into the compact model HICUM/L2. The extended model shows excellent agreement over a wide bias and temperature range with the experimental data of a large variety of SiGe HBTs from technologies of different manufacturers, including production and most advanced lab processes. View full abstract»

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  • A Correlation Between Oxygen Vacancies and Reliability Characteristics in a Single Zirconium Oxide Metal-Insulator-Metal Capacitor

    Publication Year: 2014 , Page(s): 2619 - 2627
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    A correlation between reliability characteristics and failure mechanisms for time-dependent dielectric breakdown for a single ZrO2 metal-insulator-metal capacitor has been studied. Frenkel-Poole emission was the dominant mechanism in the high electric field region. The extracted dynamic constant and trap energy level were 4.013 and 0.963 eV, respectively. The variation of α as a function of stress time under constant voltage stress (CVS) gradually decreased. Moreover, ΔCstress/C0 under dynamic voltage stress was much greater than under CVS, which indicates that new defects and charge trapping could be generated in high-κ (HK) dielectric under dynamic voltage stress under negative voltage as well as positive voltage. The extracted average value of the Weibull slope (β) at 125°C was in the range 1.3-1.6. The average field acceleration parameter was ~8.67 cm/MV, and an effective dipole moment of bond breakage peff was ~29.73e Å. The thermochemical model (E model) suggested that the oxygen vacancies induced by the dipolar energy contribution (p · Eloc) easily caused bond breakage in the HK dielectric. The energy required to form another V0 was weakened to the bond strength of polar molecules. The characteristic breakdown strength (EBD) of ZrO2 was 6.31 MV/cm, and the extracted activation energy AH0* was 1.874 eV when considering E model. View full abstract»

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  • Carbon Nanotube Nonvolatile Thin-Film Transistors With (Bi,Nd)4Ti3O12 Gate Insulators

    Publication Year: 2014 , Page(s): 2628 - 2632
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    Single-walled carbon nanotube (SWCNT) nonvolatile thin-film transistors (TFTs) with (Bi,Nd)4Ti3O12 (BNT) gate insulators were fabricated. The electrical properties of BNT films and SWCNT/BNT TFTs were investigated. The subthreshold swing, the threshold voltage, the channel mobility, and the ON/OFF ratio of SWCNT/BNT TFTs reach to 62.5 mV/decade, 0.45 V, 1.3 × 103 cm2/Vs, and 1.5 × 107, respectively. Notably, the device shows a memory window of ~4.1 V and a long retention time of ~107 s. These mainly attribute to the SWCNTs channel and BNT ferroelectric gate insulator, which induce much larger charge in channel layer. These results suggest that the SWCNT/BNT TFTs are suitable for the next-generation nonvolatile memory devices and integrated circuits. View full abstract»

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  • Accurate Prediction of Device Performance Based on 2-D Carrier Profiles in the Presence of Extensive Mobile Carrier Diffusion

    Publication Year: 2014 , Page(s): 2633 - 2639
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2358 KB) |  | HTML iconHTML  

    In this paper, we illustrate how high-resolution 2-D carrier profiles from scanning spreading resistance microscopy (SSRM) can be used to predict and understand device performance of dynamic random access memory peripheral transistors with high-k metal gate and ultrashallow junctions. In an earlier study on high-speed complementary metal-oxide-semiconductor logic, the 2-D carrier profiles from SSRM were used as the active 2-D dopant profile input to the device simulator as they are virtually identical. The extensive mobile carrier diffusion caused by the lower concentrations, however, implies a strong difference between the mobile carrier distribution and the dopant distribution such that the same approach is no longer valid. Ideally one would have to generate, based on the carrier profiles, the active dopant distribution through the inverse solution of the Poisson equation (in two dimensions) which is, however, numerically nontrivial and often leads to nonunique results. Therefore, an alternative approach is proposed here, whereby we fine-tune the process simulations such that the resulting simulated carrier profiles match the 2-D SSRM profiles. Upon reaching satisfactory agreement, the simulated profiles can be used as input for a device simulator and be used to predict sensitive device parameters such as drain-induced barrier lowering and threshold voltage rolloff. View full abstract»

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  • Modeling the Channel Charge and Potential in Quasi-Ballistic Nanoscale Double-Gate MOSFETs

    Publication Year: 2014 , Page(s): 2640 - 2646
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    In this paper, we present an analytical semiempirical model of the profile of the channel charge and potential in quasi-ballistic double-gate (DG) MOSFETs. The charge model is based on the premise of separating the charge density in the quasi-ballistic channel into two hypothetical components: 1) exclusively ballistic (collision-free) and 2) collision-dominated components, which are governed by the same electrostatics. These components are related to each other through a ballisticity parameter whose values lie between 0 and 1. Varying the value of this parameter allows us to model the charge profile continuously between diffusive and purely ballistic devices. Using the proposed charge model and the DG MOSFET electrostatics, an analytical expression for the channel potential is derived which, like the charge model, is continuous between the diffusive and ballistic regimes. View full abstract»

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  • GeTe Liner Stressor Featuring Phase-Change- Induced Volume Contraction for Strain Engineering of Sub-50-nm p-Channel FinFETs: Simulation and Electrical Characterization

    Publication Year: 2014 , Page(s): 2647 - 2655
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    We report the experimental demonstration of strained p-channel FinFETs featuring a GeTe liner stressor that exhibits very large volume contraction (~10%) during phase change. Conformally grown GeTe liner was formed on FinFETs with sub-50-nm gate length LG. When the GeTe liner changes phase from amorphous (α-GeTe) to polycrystalline (c-GeTe) state, it contracts and imparts very high compressive channel stress. A finite element method simulation was performed to study the channel stress in FinFETs, followed by a k · p calculation of Si valence band structure with the simulated strain tensors. The effective mass of the topmost valence band is reduced and the band dispersion between heavy-hole and light-hole sub-bands at Γ point increases with the effect of the strain induced by the GeTe liner. Significant drive current IDsat enhancement of 96% was observed for FinFETs with 50-nm c-GeTe liner stressor over the control devices. IDsat enhancement increases as LG reduces, showing good scalability of the GeTe liner stressor for possible application in future technology nodes. View full abstract»

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  • High-Performance Germanium p- and n-MOSFETs With NiGe Source/Drain

    Publication Year: 2014 , Page(s): 2656 - 2661
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1484 KB) |  | HTML iconHTML  

    In this paper, we report Ge pand n-channel metal- oxide-semiconductor field-effect transistors (MOSFETs) with NiGe source/drain (S/D) with high performance and low leakage current. The forward/reverse current ratio of the NiGe/n-Ge and NiGe/p-Ge junctions were ~105 and ~2 × 104 at |V| = ±1 V, respectively. Interface state densities Dit of Al2O3/GeO2/Ge stack is improved to be around 1012/eV-1 cm2 near the midgap after forming gas annealing; the gate-stack also shows excellent reliability under constant field stressing. Both p- and n-channel MOSFETs show sufficiently high ION/IOFF ratio. High driving current of ~9 and ~4 μA/μm at |VGS - VT| = ±0.8 V and |VDS| = ± V is obtained, respectively, for pand n-MOSFETs. Moreover, S/D series resistance RSD of the p- and n-MOSFET is reduced by ~25% and ~42% as compared with that of the transistors with conventional p/n junctions. View full abstract»

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  • An Ultralow EOT Ge MOS Device With Tetragonal HfO2 and High Quality HfxGeyO Interfacial Layer

    Publication Year: 2014 , Page(s): 2662 - 2667
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    A Ge MOS device with an ultralow equivalent oxide thickness of ~0.5 nm and acceptable leakage current of 0.5 A/cm2 is presented in this paper. The superior characteristics can be attributed to a tetragonal HfO2 with a higher k value (k ~ 31) and comparable bandgap. In addition, a Ge MOS device with tetragonal phase HfO2 (t-HfO2) also shows a lower leakage current and better thermal stability. The mechanisms for t-HfO2 formation may be explained by the little Ge diffusion from Ge substrate and oxygen deficiency, which are obtained by in situ interfacial layer (IL) formation and high-k processes. The IL with k ~ 13 can be formed by in situ H2O plasma treatment. Moreover, a Ge MOS device with the IL grown by H2O plasma shows smaller interface trap density and hysteresis effects due to a high composition of Ge+4. View full abstract»

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  • A Compact Model of Program Window in HfOx RRAM Devices for Conductive Filament Characteristics Analysis

    Publication Year: 2014 , Page(s): 2668 - 2673
    Cited by:  Papers (1)
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    This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices. View full abstract»

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  • Electron-Hole Bilayer TFET: Experiments and Comments

    Publication Year: 2014 , Page(s): 2674 - 2681
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3115 KB) |  | HTML iconHTML  

    We investigate Si/Si0.85Ge0.15 fully depleted-SOI tunnel FET (TFET) devices operated in the electron-hole bilayer (EHB) mode. The application of negative bias on front gate and positive bias on back gate results in confined hole and electron layers that are expected to enable vertical band-to-band tunneling (BTBT). The idea of the EHB-TFET device is to enhance the tunneling current by expanding the BTBT generation area from the narrow lateral source/channel junction to the entire channel region. Our systematic measurements on a variety of TFETs with variable geometry and channel materials do not offer support to this attractive concept. Self-consistent simulations confirm that the vertical BTBT transitions do not produce an appreciable current in our devices, due to size-and bias-induced quantization, effective mass anisotropy, and incomplete formation of the bilayer. We examine the conditions for efficient vertical BTBT to occur and show that they cannot be met simultaneously, at least in Si or Si/SiGe devices. View full abstract»

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  • Understanding and Modeling of Diode Voltage Overshoots During Fast Transient ESD Events

    Publication Year: 2014 , Page(s): 2682 - 2689
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    Diodes in forward direction exhibit excellent ESD ruggedness and are thus widely used in both discrete and on-chip electro-static discharge (ESD) protection devices. Due to the conductivity modulation under an ESD stress, a transient voltage overshoot is observed at the beginning of a fast discharge event. Since the voltage overshoot can be harmful, understanding the origin of the overshoot is crucial to design optimized protection diodes. In this paper, it will be shown that existing models can result in much underestimated overshoot voltage, especially for diodes with a large lowly doped region. This can be attributed to the negligence of transient charge distribution in the lowly doped region. A new model that takes this effect into account as well as impact-ionization is presented. View full abstract»

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  • An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs

    Publication Year: 2014 , Page(s): 2690 - 2696
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    In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified. The dual-modulation effects in TFETs that the surface potential of the channel is alternatively controlled by the gate bias and drain bias in different operating regimes are emphasized and studied. The transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively. For the first time, a closed-form analytical model of the surface potential in TFETs, including the impacts of both the gate voltage and drain voltage is proposed. Furthermore, a compact current model of the TFET-based on the derived surface potential expression is given. The model predicted tunneling current agree well with the TCAD simulation results in all operating regions of TFETs, which will be helpful for the circuit properties simulation of the TFET. View full abstract»

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  • Quantum Analytical Modeling for Device Parameters and I V Characteristics of Nanoscale Dual-Material Double-Gate Silicon-on-Nothing MOSFET

    Publication Year: 2014 , Page(s): 2697 - 2704
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    This paper presents the quantum analytical model, based on the self-consistent solution of 1-D Schrödinger equation and 2-D Poisson's equation for the ultrascaled dual-material double-gate (DMDG) silicon-on-nothing MOSFET structure. The quantum mechanical effects (QMEs) have been incorporated in our model to derive the analytical current expressions for the first time ever. Extensive calculations have been carried out to analyze the QMEs on such device performance parameters, like electric field, transconductance, drain conductance, and voltage gain. A comparative analysis based on the drain current has been presented in this paper for the classical and for the quantum model. The authenticity of our proposed quantum model for the DMDG structure is verified by the agreement among the results obtained from the analytical model as well as simulations. View full abstract»

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  • Threshold Voltage Variations Due to Oblique Single Grain Boundary in Sub-50-nm Polysilicon Channel

    Publication Year: 2014 , Page(s): 2705 - 2710
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    We investigate the effect of single grain boundary (SGB) with arbitrary angles on the threshold voltage (Vth) variation in sub-50-nm polysilicon (poly-Si) channel devices using 3-D simulation. An SGB in the poly-Si channel causes changes in potential barrier profile resulting in the variation of Vth. As the planar devices scale down to 20-nm, oblique SGB can significantly increase the whole potential barrier profile and cause large Vth variation. However, due to superior gate controllability, the gate-all-around devices show relatively small increase of the conduction energy band, and thus mitigate the Vth variation even in 20-nm poly-Si channel. View full abstract»

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  • Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology

    Publication Year: 2014 , Page(s): 2711 - 2718
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2134 KB) |  | HTML iconHTML  

    FinFET technology is prone to suffer from line edge roughness (LER)-based VT variation with scaling. It also lacks a simple implementation of multiple VT technology needed for power management. To address these challenges, in this paper we present an epitaxially defined FinFET (EDFinFET) as an alternate to FinFET architecture for nodes 15 nm and beyond. We show by statistical simulations that EDFinFET reduces overall VT variability with an 80% reduction in LER-based variability in comparison with FinFETs. We present dynamic threshold MOS (DTMOS) configuration of EDFinFET using the available body terminal to individual transistors. The DTMOS configuration reduces LER-based variability by 90% and overall variability by 59%. It also has excellent subthreshold slope (SS) and gives 43% higher ION compared with FinFETs. Meanwhile, EDFinFET shows poorer SS and lower ION than FinFET due to single gate control. However, it is capable of multiple VT, which leads to circuit level power optimization. View full abstract»

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  • Optimum Bandgap and Supply Voltage in Tunnel FETs

    Publication Year: 2014 , Page(s): 2719 - 2724
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1553 KB) |  | HTML iconHTML  

    A physics-based analytic model of the ON- and OFF-currents in a homojunction tunnel field-effect transistor (TFET) is used to understand the relationship between bandgap, gate length, ON-current, OFF-current, ON/OFF current ratio, and supply voltage to meet minimum energy requirements. The model, which applies to direct-bandgap semiconductors, is validated against numerical simulations to show that it captures the trends of more comprehensive simulations. The analytic model is then used to compare alternative channel materials for TFETs. Gate-all-around InAs nanowire and graphene nanoribbon TFETs are used as design examples at gate lengths of 10 and 15 nm and for an ON/OFF current specification of 105. The results suggest that TFETs based on 2-D materials can be more energy efficient than semiconductor nanowire TFETs and conventional metal-oxide-semiconductor field-effect transistors for low-power logic. View full abstract»

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  • Dead Time Compensation in CMOS Single Photon Avalanche Diodes With Active Quenching and External Reset

    Publication Year: 2014 , Page(s): 2725 - 2731
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    Single photon avalanche diodes (SPADs) in CMOS are becoming increasingly interesting devices for timing applications, such as fluorescence lifetime imaging, positron emission tomography, and time of flight mass spectroscopy. The CMOS allows integration of functionalities like time-to-digital converters within the same pixel, and the manufacturing of large format arrays. Dead time has to be taken into account in order to correctly interpret SPAD measurements. In this paper, we derive and test a model for dead time in real SPADs where reset is generated off-pixel. We test the model using our own custom designed devices made in a low-voltage 180-nm CMOS image sensor process with full custom implants. A Monte Carlo simulation is implemented to compare with experimental results. Using a fitting method, higher values of the photon detection efficiency (PDE) can be extracted than with a simple linear fit. The resulting PDE corrections are significant, up to 100% depending on the conditions. The limitations are approximated, and it is found that accurate predictions of the true count rate are possible over a control range of 0.25-1.0 MHz. View full abstract»

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  • A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry

    Publication Year: 2014 , Page(s): 2732 - 2737
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1844 KB) |  | HTML iconHTML  

    Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this paper, we demonstrate that using the unique quasi-linear relationship between the surface potentials, it is possible to develop compact model for CDG-MOSFETs without such approximation while preserving the mathematical complexity at the same level of the existing models. In the proposed model, the surface potential relationship is used to include the drain-induced barrier lowering, channel length modulation, velocity saturation, and quantum mechanical effect in the long-channel model and good agreement is observed with the technology computer aided design simulation results. View full abstract»

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  • Fin Shape Impact on FinFET Leakage With Application to Multithreshold and Ultralow-Leakage FinFET Design

    Publication Year: 2014 , Page(s): 2738 - 2744
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2111 KB) |  | HTML iconHTML  

    FinFETs have emerged as the solution to short channel effects at the 22-nm technology node and beyond. Previously, there have been few studies on the impact of fin cross section shape on transistor leakage. We show for the first time that fin shape significantly impacts transistor leakage in bulk tri-gate nFinFETs with thin fins when the fin body doping profile is optimized to minimize leakage. We show that a triangular fin reduces leakage current by 70% over a rectangular fin with the same base fin width. We describe how fin shape can be used to implement multithreshold nFinFETs without increasing chip area consumption. We also describe how by combining triangular fins with existing gate-source/drain underlap multithreshold techniques, it is possible to design ultralow-power nFinFETs with less than 1 pA/μm leakage current while maintaining high performing ION/IOFF, threshold voltage, and subthreshold swing. View full abstract»

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  • Problems With the Continuous Doping TCAD Simulations of Decananometer CMOS Transistors

    Publication Year: 2014 , Page(s): 2745 - 2751
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3248 KB) |  | HTML iconHTML  

    In this paper, we compare results from atomistic and continuous simulation of decananometer scale CMOS transistors. We study the behavior of important figures of merit, including threshold voltage, subthreshold slope, OFF-current, and ON-current. We provide physical explanation for the origin of the discrepancies between the averaged values obtained from the statistical simulations and the results from the continuous doping simulation. Based on our analysis, we clearly demonstrate that there are increasing errors in the doping distributions when device TCAD simulations are calibrated using continuous doping profiles. This questions the use of continuous doping profiles in the routine calibration and TCAD-based optimization of decananometer scale CMOS transistors. View full abstract»

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  • Thermal Modeling of Multi-Fin Field Effect Transistor Structure Using Proper Orthogonal Decomposition

    Publication Year: 2014 , Page(s): 2752 - 2759
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    An approach is proposed to project thermal behavior in a semiconductor integrated-circuit structure onto a functional space based on the proper orthogonal decomposition (POD). The approach substantially reduces the numerical degrees of freedom (DOF) needed for thermal simulations and requires no assumptions about physical geometry, dimensions, or heat flow paths. The POD approach is applied to a multi-fin FinFET structure having heat sources driven by power pulse excitations with time shifts, width variations, and amplitude modulations. The POD models were compared with detailed numerical simulations (DNS) and it was shown that the POD approach provides thermal solutions that were as accurate and detailed as the DNS. It offers a reduction in numerical DOFs by nearly six orders of magnitude to capture the peak temperatures in multi-fin FinFETs. View full abstract»

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  • Investigation of Temperature-Dependent Characteristics of AlGaN/GaN MOS-HEMT by Using Hydrogen Peroxide Oxidation Technique

    Publication Year: 2014 , Page(s): 2760 - 2766
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    This paper investigates the temperature-dependent performances of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT). The gate dielectric layer and surface passivation layer are formed by the H2O2 oxidation technique. The gate dielectric quality is estimated by the breakdown electric field (EBD) and low-frequency noise. The capacitance-voltage (C-V) hysteresis characteristics of MOS and Schottky diodes at 300/480 K are also studied. An appropriate thermal model is used to investigate the self-heating effect and calculate the effective channel temperature (Teff). The dc performances of the present MOS-HEMT are improved at 300/480 K, as compared with a Schottky-barrier HEMT (SB-HEMT), including output current density, maximum extrinsic transconductance (gm,max), gate voltage swing, gate-drain leakage current (IGD), specific ON-resistance (RON), three-terminal OFF-state breakdown voltage (BVOFF), and subthreshold swing. Factors that cause IGD and BVOFF are analyzed by the temperature-dependent measurement. The passivation effect of the present MOS-HEMT is also confirmed by the surface leakage measurement. The devised MOS-HEMT demonstrates superior thermal stability to the reference SB-HEMT. The present-design is promising for high-temperature electronic applications. View full abstract»

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  • P2S5/(NH4)2Sx-Based Sulfur Monolayer Doping for Source/Drain Extensions in n-Channel InGaAs FETs

    Publication Year: 2014 , Page(s): 2767 - 2773
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2937 KB) |  | HTML iconHTML  

    Ultrashallow junctions that are abrupt and have low resistance are needed for the source/drain extensions (SDEs) of MOSFETs at future technology nodes. In addition, the use of 3-D devices, such as FinFETs or nanowire FETs, will require a doping process that is conformal. In this paper, we discuss P2S5/(NH4)2Sx-based doping for potential use in the formation of SDEs for n-channel InGaAs FETs. MOSFETs with source and drain formed using this doping technique are demonstrated. The effect of the dopant activation step on device performance is also studied. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego