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Solid-State Circuits, IEEE Journal of

Issue 8 • Date Aug. 2014

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Displaying Results 1 - 23 of 23
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): C2
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  • Table of contents

    Page(s): 1665 - 1666
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  • Introduction to the Special Issue on the 2013 IEEE Custom Integrated Circuits Conference

    Page(s): 1667 - 1668
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  • A Broadband Sensor Interface IC for Miniaturized Dielectric Spectroscopy From MHz to GHz

    Page(s): 1669 - 1681
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3095 KB) |  | HTML iconHTML  

    This paper describes a broadband sensor interface IC as part of a miniaturized measurement platform for MHz-to-GHz dielectric spectroscopy. Developed in 0.35 μm 2P/4M RF CMOS, the IC measures frequency-dependent S 21 magnitude and phase of a microfluidic dielectric sensor fabricated in a thick gold-on-glass microfabrication process and loaded with a material-under-test (MUT). The IC architecture implements a broadband frequency response analysis (bFRA) method by first down-converting the sensor response signal from the RF excitation frequency to an intermediate frequency (IF) of 1 MHz using a low-noise amplifier (LNA) and active mixer, followed by down-converting the IF signal to dc using a coherent detector employing IF amplification stages with programmable gain, a passive mixer driven by in-phase (I) and quadrature-phase (Q) signals and an active-RC low-pass filter (LPF). The sensor interfaced with the IC is fully capable of differentiating among deionized (DI) water, phosphate buffered saline (PBS), ethanol and methanol in tests conducted at four different excitation frequencies of 50 MHz, 500 MHz, 1 GHz and 3 GHz. Further, dielectric readings of ethanol from the sensor interfaced with the IC at five excitation frequencies in the range of 50 MHz to 2 GHz are in excellent agreement (error <;1%) with those from using a vector network analyzer (VNA) as the sensor readout. A bulk-solution reference measurement by an Agilent 85070E dielectric probe kit interfaced with a VNA is also performed to verify proof-of-concept feasibility in conducting MHz-to-GHz dielectric spectroscopy with a miniaturized measurement platform using μL-sample volumes. View full abstract»

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  • A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes

    Page(s): 1682 - 1693
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    We propose a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. A conventional approach to generate these currents is to drop a temperature sensitive voltage across a resistor. Since a large resistance is required to achieve nWs of power consumption with typical voltage levels (100 s of mV to 1 V), we introduce a new sensing element that outputs only 75 mV to save both power and area. The sensor is implemented in 0.18 μm CMOS and occupies 0.09 mm 2 while consuming 71 nW. After 2-point calibration, an inaccuracy of + 1.5°C/-1.4°C is achieved across 0 °C to 100 °C. With a conversion time of 30 ms, 0.3 °C (rms) resolution is achieved. The sensor does not require any external references and consumes 2.2 nJ per conversion. The sensor is integrated into a wireless sensor node to demonstrate its operation at a system level. View full abstract»

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  • Sampling Circuits That Break the kT/C Thermal Noise Limit

    Page(s): 1694 - 1701
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    Several circuit-level techniques are described which are used to reduce or cancel thermal noise and break the so-called kT/C limit. kT/C noise describes the total thermal noise power added to a signal when a sample is taken on a capacitor. In the first proposed technique, the sampled thermal noise is reduced by altering the relationship between the sampling bandwidth and the dominant noise source, providing a powerful, new degree of freedom in circuit design. In the second proposed technique, thermal noise sampled on an input capacitor is actively canceled using an amplifier, so that the noise at the amplifier output can be controlled independently of input capacitor size. Measurements from two test chips are presented which demonstrate sampled thermal noise power reduction of 48% and 67%, respectively, when compared with conventional kT/C-limited sampling. View full abstract»

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  • A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications

    Page(s): 1702 - 1714
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2990 KB) |  | HTML iconHTML  

    An 82 mW fully integrated stereo ground-referenced headphone module is designed in 40 nm CMOS. Lower platform cost is enabled by integrating the headphone module on the same SoC as the baseband functions. Maintaining device reliability with direct battery hook-up and providing large output swing are major challenges for this work, and several techniques were employed to guarantee safe operation for all of the devices under various conditions. Area reduction techniques were utilized to reduce the die cost and achieve lower platform cost. The module supports direct battery hookup with a battery range from 3.1 to 4.5 V and achieves a minimum low frequency, i.e., 217 Hz, PSRR of 110 dB at the lowest battery voltage. Audio quality is preserved by achieving a dynamic range of 100 dB, THD+N of -84 dB at 10 mW output power, and 160 μV pop-and-click noise level during power-up and power-down. The module occupies an area of 0.675 mm 2 on the SoC. View full abstract»

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  • Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling

    Page(s): 1715 - 1724
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2053 KB) |  | HTML iconHTML  

    This paper proposes a blind calibration algorithm for suppressing nonlinearity in analog-to-digital converters (ADCs). The proposed algorithm does not need any external calibration signal and is first of its kind. The proposed algorithm relies on the properties of downsampling and orthogonality of sinusoidal signals to estimate the nonlinearity coefficients present in the system and can be operated to remove even and odd order nonlinearities simultaneously. The working of the algorithm is demonstrated on a first-order ring oscillator based ΔΣ ADC, whose performance is limited due to the nonlinearity present in its system. Built in 0.13 μm CMOS, the algorithm improves the SNDR of the ADC by 39 dB, while improving SFDR by 45 dB. View full abstract»

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  • A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB

    Page(s): 1725 - 1738
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    This paper presents a 12.8 GS/s 32-way hierarchically time-interleaved SAR ADC with 4.6 ENOB in 65 nm CMOS. The prototype utilizes hierarchical sampling and cascode sampler circuits to enable greater than 25 GHz 3 dB effective resolution bandwidth (ERBW). We further employ a pseudo-differential SAR ADC to save power and area. The core circuit occupies only 0.23 mm 2 and consumes a total of 162 mW from dual 1.2 V/1.1 V supplies. The design achieves a SNDR of 29.4 dB at low frequencies and 26.4 dB at 25 GHz, resulting in a figure-of-merit of 0.79 pJ/conversion-step. As will be further described in the paper, the circuit architecture used in this prototype enables expansion to 25.6 GS/s or 51.2 GS/s via additional interleaving without significantly impacting ERBW. View full abstract»

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  • A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate

    Page(s): 1739 - 1750
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1954 KB) |  | HTML iconHTML  

    A two-stage pipelined ADC employs a double-sampling residue amplifier, two interleaved precharged DACs, and a new calibration scheme to correct for residue gain error, offset, and nonlinearity. The coarse and fine stages are implemented as flash ADCs incorporating several techniques to reduce their power, complexity, and kickback noise. Realized in 65 nm CMOS technology and sampling at 1 GHz, the prototype achieves an SNDR of 48 dB at the Nyquist rate and exhibits an FOM of 25 fJ/conversion-step while drawing 7.1 mW from a 1 V supply. View full abstract»

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  • An 8 Bit 4 GS/s 120 mW CMOS ADC

    Page(s): 1751 - 1761
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2611 KB) |  | HTML iconHTML  

    A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology. View full abstract»

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  • An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

    Page(s): 1762 - 1772
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1733 KB) |  | HTML iconHTML  

    Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multibit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although its spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in-band phase noise of -103 dBc/Hz and power consumption of 4.2 mW. View full abstract»

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  • A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

    Page(s): 1773 - 1784
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3002 KB) |  | HTML iconHTML  

    A 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots. While most previously reported peaking-free PLLs require additional circuit components which may adversely affect clock jitter or increase hardware complexity, the presented PLL requires only a new type of digital loop filter. The analysis on the loop dynamics and design of the optimal loop filter are presented. As for the implementation, a low-power linear time-to-digital converter (TDC) is realized with a set of three binary phase-frequency detectors whose triggering clocks are dithered using a delta-sigma modulator and phase interpolators. A digitally controlled oscillator (DCO) is implemented as a transformer-tuned LC oscillator whose frequency is set by a ratio between two digitally controlled currents. The digital PLL prototype, fabricated in a 65 nm CMOS, demonstrates 1.2 ps rms integrated jitter at 9.2 GHz and 1.58 μs settling time with 700 kHz bandwidth while dissipating 63.9 mW at a 1.2 V nominal supply. View full abstract»

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  • A 21–48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications

    Page(s): 1785 - 1799
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    This paper presents a mm-wave subharmonic injection-locked (SHIL) fractional-N frequency synthesizer for wireless multiband point-to-point backhaul communications. The SHIL synthesizer implements a low-phase-noise 4.5-6.1 GHz PLL and injects its output to a ÷3/÷4 dual-modulus divider followed by an ultra-wideband injection-locked frequency-multiplier (ILFM) chain to achieve excellent phase noise over an ultra-wide frequency tuning range. The proposed ILFM chain employs higher-order LC tanks to generate a rippled phase response around 0 ° over a wide frequency range to significantly enhance the locking range and to eliminate expensive mm-wave frequency calibration loops. Fabricated in a 65 nm CMOS process, the synthesizer prototype measures a continuous output frequency range from 20.6 to 48.2 GHz with frequency resolution of 220 kHz and output phase noise between -107.0 and -113.9 dBc/Hz at 1 MHz offset while consuming 148 mW and occupying 1850 × 1130 μm 2. View full abstract»

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  • Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming

    Page(s): 1800 - 1814
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    We introduce a ladder filter-based programmable time-delay element for beamforming in ultra-wideband (UWB) systems. Such a lumped-element realization becomes possible by approximating e-std as a ratio of polynomials (based on Taylor and Padé expansions). When compared with conventional methods based on the tapped delay-line architecture, the proposed technique achieves lower power dissipation, higher delay range and resolution, and better area efficiency. A prototype delay line designed for the 3.1-10.6 GHz UWB range achieves a delay range of 140 ps and a gain range of -30 dB to +10 dB. Fabricated in a 0.25 μm SiGe BiCMOS process, the delay element occupies an active area of 1 mm2 and consumes 53 mW from a 2.5 V supply. A four-antenna beamforming system using the delay element can achieve a scanning range of ±61° with 0.86 ° resolution for an antenna spacing of 15 mm. View full abstract»

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  • A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration

    Page(s): 1815 - 1826
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    A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band RF path (0.4-3 GHz) using 8-phase passive mixers and a high-band RF path (3-6 GHz) using 4-phase passive mixers. DC-offset, IIP 2, and harmonic recombination for harmonic rejection may be calibrated to achieve true wideband specifications. A 0.5-50 MHz tunable baseband bandwidth implies compliance with LTE and future standards. Despite having a 0.9 V supply, the receiver architecture ensures high out-of-band linearity. The 0.6 mm2, 28 nm CMOS receiver achieves down to 1.8 dB NF, >+3 dBm out-of-band IIP3, >70 dB calibrated HR3/5 and >+80 dBm calibrated IIP2. It tolerates 0 dBm blockers at 80 MHz offset with a blocker NF of 10 dB for a power consumption of 20-40 mW. View full abstract»

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  • A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis

    Page(s): 1827 - 1836
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    In this paper, we present a time-based equalization scheme to implement transmit de-emphasis in voltage-mode drivers. Using two-level pulse-width modulation, this work decouples the tradeoff between impedance matching, output swing, and de-emphasis resolution in conventional voltage-mode drivers using voltage-based de-emphasis. A prototype PWM-based 5 Gb/s voltage-mode transmitter was implemented in a 90 nm CMOS process and characterized across different channels and output swings. The horizontal/vertical eye opening (BER=10-12) at the end of 60 and 96 in stripline channels is 78 mv/0.6 UI and 8 mV/0.3 UI, respectively. Duty cycle distortion of the clock severely reduced the margins, so the overall performance can be improved by applying duty-cycle correction to clock signals. The transmitter consumes a total power 15.6 mW of which 2.5 mW is consumed in the digital PLL and 7.8 mW in the pre-/output drivers and regulators. This translates to a power efficiency of 3.1 mW/Gb/s, which compares favorably with the state of the art. View full abstract»

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  • A Monolithic Digital Ripple-Based Adaptive-Off-Time DC-DC Converter With a Digital Inductor Current Sensor

    Page(s): 1837 - 1847
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    A ripple-based digital controller requires inductor current ripple as feedback signals and analog RC inductor current sensors can be used for sensing the ripple. However, the passive RC components are bulky to integrate on-chip and the digital controller cannot use the analog ripple for the control purpose unless extra ADCs are available to quantize the signal. Therefore, a digital inductor current sensor is presented in this paper for obtaining the ripple in the digital domain. As compared to the existing designs, the digital inductor current sensor does not require extra ADCs or knowledge of the inductor DCR. A ripple-based digital controller is designed to demonstrate how the digital sensor can be utilized. A digital frequency-lock-loop is also incorporated into the digital controller to alleviate the problem of variable switching-frequency that is commonly found in the ripple-based control scheme. Both the digital sensor and controller are fabricated in UMC 0.13 μm digital CMOS process with a small chip area of 220 μm×220 μm. Measurements results show that a 2 MHz (max. ±6.5% in variation) buck converter achieves load-transient responses of about 5 μs by using the digital controller. The peak efficiency is 91% at a nominal load current of 100 mA. View full abstract»

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  • A 40 V 10 W 93%-Efficiency Current-Accuracy-Enhanced Dimmable LED Driver With Adaptive Timing Difference Compensation for Solid-State Lighting Applications

    Page(s): 1848 - 1860
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    This paper presents a floating-buck dimmable LED driver for solid-state lighting applications. In the proposed driver, an adaptive timing difference compensation (ATDC) is developed to adaptively adjust the off-time of the low-side power switch to enable the driver to achieve high accuracy of the average LED current over a wide range of input voltages and number of output LED loads, fast settling time, and high operation frequency. The power efficiency benefits from the capabilities of using synchronous rectifier and having no sensing resistor in the power stage. The synchronous rectification under high input supply voltage is enabled by a proposed high-speed and low-power gate driver with pseudo-digital level shifters. Implemented in a 0.35 μm 50 V CMOS process, experimental results show that the proposed LED driver can operate at 1 MHz and achieve peak power efficiency of 93% to support a wide range of series-connected output LEDs from 1 to 10 and a wide input range from 10 to 40 V. The proposed LED driver has only 2.8% current error from the average LED current of 345 mA and settles within 8.5 μs after triggering the dimming condition, improving the settling time by 14 times compared with the state-of-the-art LED drivers. View full abstract»

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  • A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications

    Page(s): 1861 - 1871
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    Embedded nonvolatile memory (eNVM) is considered to be a critical building block in future system-on-chip and microprocessor systems. Various eNVM technologies have been explored for high-density applications including dual-poly embedded flash (eflash), FeRAM, STT-MRAM, and RRAM. On the other end of the spectrum, logic-compatible eNVM such as e-fuse, anti-fuse, and single-poly eflash memories have been considered for moderate-density low-cost applications. In particular, single-poly eflash memory has been gaining momentum as it can be implemented in a generic logic process while supporting multiple program-erase cycles. One key challenge for single-poly eflash is enabling bit-by-bit re-write operation without a boosted bitline voltage as this could cause disturbance issues in the unselected wordlines. In this work, we present details of a bit-by-bit re-writable eflash memory implemented in a generic 65 nm logic process which addresses this key challenge. The proposed 6 T eflash memory cell can improve the overall cell endurance by eliminating redundant program/erase cycles while preventing disturbance issues in the unselected wordlines. We also provide details of special high voltage circuits such as a voltage-doubler based charge pump circuit and a multistory high-voltage switch, for generating a reliable high-voltage output without causing damage to the standard logic transistors. View full abstract»

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  • 2015 IEEE Radio Frequency Integrated Circuits Symposium

    Page(s): 1872
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  • IEEE Journal of Solid-State Circuits information for authors

    Page(s): C3
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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan