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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • May 1994

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Displaying Results 1 - 14 of 14
  • Correction to "Boundary single-layer routing with movable terminals"

    Publication Year: 1994
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (101 KB)

    In boundary single-layer routing with slidable or permutable terminals (BSLR-S or BSLR-P), the assumption that each net may have more than one terminal in a range or cluster should be removed. An example that shows Pick-Closest might report "unsolvable" for a solvable instance is considered. It is clear that the instance is solvable if (and only if) the two terminals of net N/sub 1/ are assigned t... View full abstract»

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  • A portable parallel algorithm for logic synthesis using transduction

    Publication Year: 1994, Page(s):566 - 580
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1096 KB)

    Combinational logic synthesis is a very important phase of VLSI system design. But the logic synthesis process requires large computing times if near optimal quality of the logic network is desired. Parallel processing is fast becoming an attractive solution to reduce the computational time. Recently, researchers have started to investigate parallel algorithms for problems in logic synthesis and v... View full abstract»

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  • Identification of redundant delay faults

    Publication Year: 1994, Page(s):553 - 565
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB)

    Various defects during fabrication have been shown in the literature to introduce delay faults in logic circuits. This paper analyzes the effects of these defects on the normal operation of logic circuits with the goal of developing an appropriate model for these faults. Single and multiple delay faults in this model are analyzed to determine if they are redundant with respect to the normal operat... View full abstract»

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  • Functional synthesis of digital systems with TASS

    Publication Year: 1994, Page(s):537 - 552
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    Synthesizing a digital system from a functional description is a complex process requiring the solution of various different problems. TASS (Tabu Search Synthesis System) is a functional synthesis system made up of interdependent modules based on new and more efficient algorithms. First, a control and data flow graph model for system representation is developed and presented. This model generates ... View full abstract»

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  • Analytical MOSFET model for quarter micron technologies

    Publication Year: 1994, Page(s):610 - 615
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    For deep submicron MOSFET's short-channel effects dominate the transistor characteristics. We present here a new analytical MOSFET model for circuit simulation which includes these effects. The model is based on the charge-sheet approximation including the drift and the diffusion contributions. Additionally the model includes the contribution of the lateral electric field explicitly. Therefore it ... View full abstract»

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  • Fault secure property versus strongly code disjoint checkers

    Publication Year: 1994, Page(s):651 - 658
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The final checker of a self-checking system is an embedded double-rail checker (the partial checkers have in general two outputs). The self-testing or the strongly code disjoint property of this embedded checker can be lost if it is not exercised by an appropriate set of inputs. If some partial checkers are strongly code disjoint, then some undetectable faults can modify the input/output mapping o... View full abstract»

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  • Optimization of state encoding in distributed circuits

    Publication Year: 1994, Page(s):581 - 588
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Delay-insensitive (DI) circuits are a class of asynchronous circuit whose functional correctness is unaffected by component delays or wire delays. DI circuits can be considered as distributed circuits in which the system is protocol based and no global information is available. Existing truly DI implementations of state machines have so far required area which is linearly proportional to the numbe... View full abstract»

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  • Algorithms for simulation of three-dimensional etching

    Publication Year: 1994, Page(s):616 - 624
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    A three-dimensional optical lithography simulator has been developed based on a new ray-string algorithm for dissolution etch-front advancement. In developing the new algorithm, performance studies of cell, string and ray algorithms were carried out in two dimensions. A key finding was that a recursive ray method for the calculation of the surface-advancement vector produced numerically stable and... View full abstract»

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  • Hierarchical analysis of high frequency interconnect networks

    Publication Year: 1994, Page(s):658 - 664
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    Interconnect networks are analyzed using symbolic frequency domain analysis and an exact model of a distributed line. The analyzed network must have a tree structure and may contain transmission lines as well as other linear two-ports with specified transmission matrices. Any regular portion of the interconnect network is analyzed hierarchically with significant savings in analysis time. Numerical... View full abstract»

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  • Satisfaction of input and output encoding constraints

    Publication Year: 1994, Page(s):589 - 602
    Cited by:  Papers (21)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1136 KB)

    Three encoding problems relevant to the synthesis of digital circuits are input, output, and state encoding. Several encoding strategies have been proposed in the past that decompose the encoding problem into a two step process of constraint generation and constraint satisfaction. The latter requires the assignment of binary codes to symbols subject to the satisfaction of constraints on the codes.... View full abstract»

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  • SWiTEST: a switch level test generation system for CMOS combinational circuits

    Publication Year: 1994, Page(s):625 - 637
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB)

    Switch level test generation (SLTG) is potentially more powerful than conventional gate level test generation (GLTG) or CMOS circuits. Over the last decade much research has been carried out on SLTG. However to date no widely accepted SLTG system exists. The objectives of this work are to analyze the various problems associated with SLTG, to identify a feasible way to deal with these problems, and... View full abstract»

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  • Optimal algorithms for bubble sort based non-Manhattan channel routing

    Publication Year: 1994, Page(s):603 - 609
    Cited by:  Papers (8)  |  Patents (68)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    It has been pointed out that, in many cases, results generated by non-Manhattan channel routers will be better than those generated by Manhattan routers. Non-optimal bubble sort based algorithms for non-Manhattan channel routing have been proposed in the literature by also allowing connections in the +45° and -45° directions. In this paper, optimal algorithms are proposed for the two-layer... View full abstract»

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  • Reducing correlation to improve coverage of delay faults in scan-path design

    Publication Year: 1994, Page(s):638 - 646
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    Simulation data are presented for eleven benchmark circuits to show how test pattern correlation in a scan-path design circuit adversely affects delay fault coverage, and to demonstrate that most undetected delay faults caused by correlation of test patterns are close to the outputs of latches. Topology-based latch correlation measures are introduced and used by a companion latch arrangement algor... View full abstract»

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  • Redundancy identification and removal in combinational circuits

    Publication Year: 1994, Page(s):646 - 651
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    Identification and removal of redundancy in digital circuits is important for improving their testability as well as reducing their area. This paper presents a method of identifying and removing redundancy in combinational circuits by analyzing circuit structure. Experimental results indicate that the method is quite efficient in execution time, but may not identify all undetectable faults. It is ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu