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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 7 • Date July 2014

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Displaying Results 1 - 23 of 23
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

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  • A Thermometer-Like Mismatch Shaping Technique With Minimum Element Transition Activity for Multibit \Delta \Sigma DACs

    Page(s): 461 - 465
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1174 KB) |  | HTML iconHTML  

    This brief presents a novel mismatch shaping technique for multibit delta-sigma digital-to-analog converters (DACs). It uses the intrinsic quantization noise to randomize the element selection. Different from most existing mismatch shaping techniques that increase the element transition activity, the proposed technique keeps the same transition rate as that for the basic thermometer coding scheme. As a result, it produces much lower intersymbol interference (ISI)-induced distortions. Moreover, it does not produce tones and can high-pass shape the mismatch errors, unlike thermometer coding that produces large distortions due to static mismatch. An efficient hardware implementation based on the vector-quantizer mismatch shaping framework is also presented. Simulations show that the proposed technique can significantly improve DAC linearity in the presence of both ISI and mismatch errors. View full abstract»

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  • A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS

    Page(s): 466 - 470
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (900 KB) |  | HTML iconHTML  

    This brief presents an improved timing scheme for a 4× interleaved 6-bit pipelined binary search (PLBS) analog-to-digital converter (ADC). The individual channel consists of a calibrated fully dynamic PLBS architecture with a 1-bit folding front-end. This work enhances the ADC conversion rate up to 3.5 GS/s, for 4.1-mW power consumption. The peak spurious-free dynamic range and signal-to-noise-plus-distortion ratio (SNDR) are 44.1 and 31.2 dB, respectively, measured for low input frequency. With near-Nyquist input frequency, the SNDR drops to 29.5 dB, yielding an energy-per-conversion step of 48 fJ. The prototype has been fabricated in a 40-nm low-power digital CMOS process. The ADC active area is 250 × 120 μm2. View full abstract»

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  • A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1–1.5-GHz Multistandard Applications

    Page(s): 471 - 475
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1757 KB) |  | HTML iconHTML  

    A reconfigurable dual-mode power amplifier (PA) with an integrated transmit/receive (T/R) switch in 65-nm CMOS is presented. The PA can be reconfigured into linear mode or switching mode. In the linear mode, it achieves >19 dBm OP1 dB with >20% PAE over 0.1-1.5 GHz; in the switching mode, the maximum saturation output power of 23.2 dBm with the peak PAE of 60% is obtained. By utilizing the asymmetrical topology and stacked techniques, the T/R switch demonstrates ~0.5-dB TX insertion loss, >27-dB TX-RX isolation, and 24.8 dBm IP1 dB across 0.1-1.5 GHz. This brief proposes, for the first time, a CMOS dual-mode PA with an integrated T/R switch for multistandard applications. View full abstract»

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  • Optimizing the Stage Resolution in Pipelined SAR ADCs for High-Speed High-Resolution Applications

    Page(s): 476 - 480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (745 KB) |  | HTML iconHTML  

    The successive approximation register (SAR) analog-to-digital converters (ADCs) outperform other types of ADCs on the area and energy efficiency due to its binary searching algorithm, which however has a conversion speed limitation. When pipelining multiple SAR ADCs, the speed is improved, the resolutions in individual stages are relaxed, and the nonidealities from non-first stages are desensitized by the gains preceding them. This brief examines the effects of the stage resolution on linearity, noise, speed, area, and power consumption in pipelined SAR ADCs. Two conclusions are reached. First, under certain cases, a larger resolution per stage improves the ADC linearity without costing the speed of the operational amplifiers (op-amps) used for residue amplifications. However, the stage resolution does not affect the op-amp open-loop gain requirement. Second, for area and power consideration, allocating about one quarter of the overall number of bits to the first stage is optimum in the practical situation that the area and power of the active circuitries are tens or hundreds of times of those of the unit capacitors in the SAR sub-ADCs. View full abstract»

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  • Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

    Page(s): 481 - 485
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1054 KB) |  | HTML iconHTML  

    Analysis of an open-loop time amplifier shows good agreement between measurements and calculations on the time gain, distortion of time gain, and rms noise and offset of output time difference. The time amplifier is based on the slew rate control method. It achieves a large time gain up to 120 and a wide range of input time difference up to 2 ns. The circuit consists of two precharged capacitors and current sources, where one capacitor is discharged at a fast slew rate during the time interval of the input time difference and then both capacitors are discharged at the same slow slew rate. The time gain is simply determined by the ratio of two bias current values. The proposed time amplifier is followed by an 8-bit TDC to obtain the digital output code. The time gain distortion caused by channel length modulation is less than 1.6% for the input time difference larger than 100 ps. The time offset and the rms noise of output time difference are inversely proportional to the smaller bias current. The rms noise is dominated by the noise of the comparator reference voltage. The time amplifier and TDC consume 0.36 mW and 1 mW, respectively, at 1.2 V supply in a 0.13 μm CMOS process. View full abstract»

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  • A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs

    Page(s): 486 - 490
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (771 KB) |  | HTML iconHTML  

    A digital calibration scheme is proposed to minimize the timing mismatch in time-interleaved analog-to-digital converters (TIADCs). First, the scheme is to subtract the outputs from adjacent channel ADCs and to utilize the expectations of the absolute value of the subtracted results to represent the actual sampling time interval. The timing mismatch is recognized by comparing these expectations. The obtained information is fed back to adjust variable delay buffers, thus reducing the timing mismatch. The application of this scheme to a 12-bit 1.6 GS/s four-channel TIADC is demonstrated. Simulation results show that with an input signal whose bandwidth is limited to the Nyquist frequency, the proposed timing mismatch calibration scheme is effective and capable of reducing the mismatch to the minimum. Compared with traditional calibration schemes, the proposed scheme is more feasible to implement and consumes less power and chip area. View full abstract»

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  • How Can the Hysteresis Loop of the Ideal Memristor Be Pinched?

    Page(s): 491 - 495
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (614 KB) |  | HTML iconHTML  

    The hysteresis loop pinched at the origin of the v-i characteristic is the well-known fingerprint of the memristor excited by sinusoidal signal. This brief generalizes the present knowledge of the parameters of the pinched hysteresis loop for a periodical zero-dc driving signal described by an odd function of time. This brief concurrently brings new relationships between the parameter versus state map characteristics, the type of the excitation, and the type of loop pinching. View full abstract»

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  • Temperature Sensor Front End in SOI CMOS Operating up to 250 ^{\circ}\hbox {C}

    Page(s): 496 - 500
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (773 KB) |  | HTML iconHTML  

    This brief presents a complementary-to-absolute-temperature voltage and a voltage reference based on the threshold voltage Vth extraction principle. The proposed Vth extraction circuit eliminates the nonlinear temperature-dependent mobility and mobility ratio terms, and it achieves a wide operating temperature range from -25 °C to 250 °C. The threshold-voltage temperature coefficient (TC) mismatch between nMOS and pMOS is compensated by selecting different channel lengths. Fabricated in the 1-μm partially depleted silicon-on-insulator CMOS process, the voltage reference achieves a box model TC of 27 parts per million (ppm) (mean) for an operating temperature range of -25 °C-250 °C and 18.7 ppm (mean) for a range of 25 °C-150 °C. Furthermore, the ratiometric output achieves mean temperature inaccuracy within ±1.8% over a temperature of 275 °C. View full abstract»

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  • Energy Harvesting Using Substrate Photodiodes

    Page(s): 501 - 505
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB) |  | HTML iconHTML  

    A circuit that is able to harvest energy from substrate/well photodiodes fabricated in standard complimentary metal-oxide-semiconductor (CMOS) processes is presented. The motivation for using substrate/well photodiodes over diffusion/well photodiodes for energy harvesting are the increased quantum efficiency due to deeper junctions, the elimination of the parasitic diode effect, and better silicon area utilization. Moreover, since substrate photodiodes also work as light sensors, they provide a new solution to self-powered image sensors. The proposed circuit uses an inductor to transfer energy from the photodiode to the load and, in the process, boosts the relatively low photodiode voltage to high levels. An analytical model of the proposed energy harvesting circuit is developed. The model is used to gain insight into the factors limiting the conversion efficiency. As a proof of concept, a test microchip was fabricated in the 0.5-μm CMOS technology. Measurements from the test microchip validate the proposed circuit and the developed analytical model. View full abstract»

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  • General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators

    Page(s): 506 - 510
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (903 KB) |  | HTML iconHTML  

    This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC)'s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDM's digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jitter-induced CTSDM's output power spectral density is simple and includes the effects of the following: 1) quantization noise power; 2) input signal power and frequency; 3) CTSDM's quantization noise transfer function; 4) DAC's pulse shape; and 5) colored jitter. A third-order CTSDM is analyzed as a test bed. Excellent agreement between theoretical predictions and behavioral simulations is observed. View full abstract»

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  • Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter

    Page(s): 511 - 515
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (675 KB) |  | HTML iconHTML  

    This brief presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite-impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM and the RAM-based LUT is found to be costly for ASIC implementation. Therefore, a shared-LUT design is proposed to realize the DA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage. The proposed design has nearly 68% and 58% less area-delay product and 78% and 59% less energy per sample than the DA-based systolic structure and the carry save adder (CSA)-based structure, respectively, for the ASIC implementation. A distributed-RAM-based design is also proposed for the field-programmable gate array (FPGA) implementation of the reconfigurable FIR filter, which supports up to 91 MHz input sampling frequency and offers 54% and 29% less the number of slices than the systolic structure and the CSA-based structure, respectively, when implemented in the Xilinx Virtex-5 FPGA device (XC5VSX95T-1FF1136). View full abstract»

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  • Write Pattern Format Algorithm for Reliable NAND-Based SSDs

    Page(s): 516 - 520
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (489 KB) |  | HTML iconHTML  

    This brief presents and evaluates a pre-coding algorithm to reduce power consumption and improve data retention in NAND-based solid-state drives. Compared to the state-of-the-art asymmetric coding and stripe pattern elimination algorithm, the proposed write pattern format algorithm (WPFA) achieves better data retention while consuming less power. The hardware for WPFA is simpler and requires less circuitry. The performance of WPFA is evaluated by both computer simulations and field-programmable gate array implementation. View full abstract»

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  • Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder

    Page(s): 521 - 525
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (475 KB) |  | HTML iconHTML  

    Floating point (F.P.) addition is a core operation for a wide range of applications. This brief presents an area-efficient, dynamically configurable, multiprecision architecture for F.P. addition. We propose an architecture of a double precision (DP) adder, which also supports a dual (two parallel) single precision (SP) computational feature. Key components involved in the F.P. adder architecture, such as comparator, swap, dynamic shifters, leading one-detector (LOD), mantissa adders/subtractors, and rounding circuit, have been redesigned to efficiently enable resource sharing for both precision operands with minimal multiplexing circuitry. The proposed design supports both normal and sub-normal numbers. The proposed architecture has been synthesized for OSUcells Cell 0.18 μm technology ASIC implementation. Compared to a standalone DP adder with two SP adders, the proposed unified architecture can reduce the hardware resources by ≈ 35%, with a minor delay overhead. Compared to previous works, the proposed dual mode architecture has 40% smaller area × delay, and has better area and delay overhead over only DP adder. View full abstract»

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  • Accurate Fixed-Point Logarithmic Converter

    Page(s): 526 - 530
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (791 KB) |  | HTML iconHTML  

    The hardware computation of the logarithm function is required in several applications, ranging from signal and image processing to telecommunication systems. This brief shows that most of previous proposed logarithmic converters, based on piecewise linear approximations, suffer from large errors when dealing with fixed-point input values with many fractional bits, a situation often encountered in practical applications. Thus, this brief proposes a novel logarithmic converter, using nonuniform segmentation and piecewise linear approximation. A rigorous technique that allows computing the optimal segmentation and the coefficients values for a prescribed precision is described in this brief. For fixed-point input values, the proposed approach allows obtaining a sensibly lower error, for the same number of nonuniform segments, compared with previously published results. Implementation details and synthesis results in a 65-nm CMOS technology are also presented. View full abstract»

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  • Energy Efficient MIMO Relay Transmissions via Joint Power Allocations

    Page(s): 531 - 535
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    The energy efficient joint source-relay power allocation problem is studied for the multi-input multi-output (MIMO) amplify-and-forward two-hop relaying system, in which the objective of the optimization is the number of the bits per second per hertz per Joule with the guarantee of the minimum spectral efficiency (SE). By assuming perfect channel state information at the transmitter, the MIMO channel is divided into several single-input single-output (SISO) subchannels via singular value decomposition (SVD). The problem is first established as an optimization subject to the minimum SE constraint, in which it is observed that both of the cost function and the constraint are not convex. By employing the high signal-to-noise ratio (SNR) approximation, the problem becomes suddenly a pseudo-convex optimization problem. Yet, the difficulty comes from solving the final Lagrangian equation, which is tackled by our proposed relaxation method according to the Jensen inequality. Finally, the analytical expression is derived for the energy efficient power allocations of the multiple antennas at the source and at the relay. Simulations demonstrate the effectiveness of the proposed method. View full abstract»

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  • Set-Membership NLMS Algorithm With Robust Error Bound

    Page(s): 536 - 540
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (855 KB) |  | HTML iconHTML  

    A new robust error bound for the set-membership normalized least mean square (SMNLMS-REB) is proposed in this brief. The new robust set-membership error bound leads to improved robustness against impulsive noise and steady-state misalignment relative to those achieved in the set-membership normalized least mean square (SMNLMS) algorithm. Stability analysis shows that the proposed algorithm is stable. Using the individual weight error variance (IWV) analysis method, new expressions for the steady-state mean square deviation (MSD) of the SMNLMS-REB are also obtained. Simulation results on system identification show that the robustness and probability of the update (PU) of the proposed SMNLMS-REB considerably outperform the traditional SMNLMS and other robust set-membership NLMS algorithms in the presence of impulsive noise. View full abstract»

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  • Pinning Controllability Analysis of Complex Networks With a Distributed Event-Triggered Mechanism

    Page(s): 541 - 545
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (739 KB) |  | HTML iconHTML  

    Pinning control synchronization of complex networks is a fascinating and hot issue in the field of nonlinear science. However, the existing works are all based on a continuous-time feedback control strategy and assume that each network node can have continuous access to the states of its neighbors. This brief presents a novel distributed event-triggered mechanism for pinning control synchronization of complex networks. The control of nodes is only triggered at their own event time, which effectively reduces the frequency of controller updates compared with continuous-time feedback control. Considering limited communication, the new approach successfully avoids the continuous communication used for calculating the error thresholds in the event-triggered mechanism. In addition, we also develop a new alternative iterative algorithm that can further reduce the consumption of computing and communication resources to some extent. Finally, simulation results show the effectiveness of the proposed approaches and illustrate the correctness of the theoretical results. View full abstract»

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  • IEEE xplore digital library

    Page(s): 546
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  • 2014 IEEE membership application

    Page(s): 547 - 548
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    Freely Available from IEEE
  • IEEE Circuits and Systems Society Information

    Page(s): C3
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

    Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope