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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 7 • Date July 2014

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Displaying Results 1 - 23 of 23
  • Table of contents

    Publication Year: 2014 , Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2014 , Page(s): C2
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  • A Thermometer-Like Mismatch Shaping Technique With Minimum Element Transition Activity for Multibit \Delta \Sigma DACs

    Publication Year: 2014 , Page(s): 461 - 465
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1174 KB) |  | HTML iconHTML  

    This brief presents a novel mismatch shaping technique for multibit delta-sigma digital-to-analog converters (DACs). It uses the intrinsic quantization noise to randomize the element selection. Different from most existing mismatch shaping techniques that increase the element transition activity, the proposed technique keeps the same transition rate as that for the basic thermometer coding scheme.... View full abstract»

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  • A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS

    Publication Year: 2014 , Page(s): 466 - 470
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (900 KB) |  | HTML iconHTML  

    This brief presents an improved timing scheme for a 4× interleaved 6-bit pipelined binary search (PLBS) analog-to-digital converter (ADC). The individual channel consists of a calibrated fully dynamic PLBS architecture with a 1-bit folding front-end. This work enhances the ADC conversion rate up to 3.5 GS/s, for 4.1-mW power consumption. The peak spurious-free dynamic range and signal-to-no... View full abstract»

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  • A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1–1.5-GHz Multistandard Applications

    Publication Year: 2014 , Page(s): 471 - 475
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1757 KB) |  | HTML iconHTML  

    A reconfigurable dual-mode power amplifier (PA) with an integrated transmit/receive (T/R) switch in 65-nm CMOS is presented. The PA can be reconfigured into linear mode or switching mode. In the linear mode, it achieves >19 dBm OP1 dB with >20% PAE over 0.1-1.5 GHz; in the switching mode, the maximum saturation output power of 23.2 dBm with the peak PAE of 60% is obtained. By utilizing the a... View full abstract»

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  • Optimizing the Stage Resolution in Pipelined SAR ADCs for High-Speed High-Resolution Applications

    Publication Year: 2014 , Page(s): 476 - 480
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (745 KB) |  | HTML iconHTML  

    The successive approximation register (SAR) analog-to-digital converters (ADCs) outperform other types of ADCs on the area and energy efficiency due to its binary searching algorithm, which however has a conversion speed limitation. When pipelining multiple SAR ADCs, the speed is improved, the resolutions in individual stages are relaxed, and the nonidealities from non-first stages are desensitize... View full abstract»

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  • Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

    Publication Year: 2014 , Page(s): 481 - 485
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1054 KB) |  | HTML iconHTML  

    Analysis of an open-loop time amplifier shows good agreement between measurements and calculations on the time gain, distortion of time gain, and rms noise and offset of output time difference. The time amplifier is based on the slew rate control method. It achieves a large time gain up to 120 and a wide range of input time difference up to 2 ns. The circuit consists of two precharged capacitors a... View full abstract»

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  • A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs

    Publication Year: 2014 , Page(s): 486 - 490
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (771 KB) |  | HTML iconHTML  

    A digital calibration scheme is proposed to minimize the timing mismatch in time-interleaved analog-to-digital converters (TIADCs). First, the scheme is to subtract the outputs from adjacent channel ADCs and to utilize the expectations of the absolute value of the subtracted results to represent the actual sampling time interval. The timing mismatch is recognized by comparing these expectations. T... View full abstract»

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  • How Can the Hysteresis Loop of the Ideal Memristor Be Pinched?

    Publication Year: 2014 , Page(s): 491 - 495
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (614 KB) |  | HTML iconHTML  

    The hysteresis loop pinched at the origin of the v-i characteristic is the well-known fingerprint of the memristor excited by sinusoidal signal. This brief generalizes the present knowledge of the parameters of the pinched hysteresis loop for a periodical zero-dc driving signal described by an odd function of time. This brief concurrently brings new relationships between the parameter versus state... View full abstract»

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  • Temperature Sensor Front End in SOI CMOS Operating up to 250 ^{\circ}\hbox {C}

    Publication Year: 2014 , Page(s): 496 - 500
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (773 KB) |  | HTML iconHTML  

    This brief presents a complementary-to-absolute-temperature voltage and a voltage reference based on the threshold voltage Vth extraction principle. The proposed Vth extraction circuit eliminates the nonlinear temperature-dependent mobility and mobility ratio terms, and it achieves a wide operating temperature range from -25 °C to 250 °C. The threshold-voltage temperature coefficient... View full abstract»

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  • Energy Harvesting Using Substrate Photodiodes

    Publication Year: 2014 , Page(s): 501 - 505
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (556 KB) |  | HTML iconHTML  

    A circuit that is able to harvest energy from substrate/well photodiodes fabricated in standard complimentary metal-oxide-semiconductor (CMOS) processes is presented. The motivation for using substrate/well photodiodes over diffusion/well photodiodes for energy harvesting are the increased quantum efficiency due to deeper junctions, the elimination of the parasitic diode effect, and better silicon... View full abstract»

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  • General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators

    Publication Year: 2014 , Page(s): 506 - 510
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (903 KB) |  | HTML iconHTML  

    This brief describes a framework for the analysis of continuous-time sigma-delta (ΣΔ) modulators (CTSDM) in the presence of a feedback digital-to-analog converter (DAC)'s clock jitter using the discrete-time Volterra series. A time-domain mixing operation between jitter and CTSDM's digital output sequence is modeled with a second-order Volterra operator. The resulting closed-form jit... View full abstract»

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  • Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter

    Publication Year: 2014 , Page(s): 511 - 515
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (675 KB) |  | HTML iconHTML  

    This brief presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite-impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM and the RAM-based LUT is found to be costly for ... View full abstract»

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  • Write Pattern Format Algorithm for Reliable NAND-Based SSDs

    Publication Year: 2014 , Page(s): 516 - 520
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (489 KB) |  | HTML iconHTML  

    This brief presents and evaluates a pre-coding algorithm to reduce power consumption and improve data retention in NAND-based solid-state drives. Compared to the state-of-the-art asymmetric coding and stripe pattern elimination algorithm, the proposed write pattern format algorithm (WPFA) achieves better data retention while consuming less power. The hardware for WPFA is simpler and requires less ... View full abstract»

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  • Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder

    Publication Year: 2014 , Page(s): 521 - 525
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (475 KB) |  | HTML iconHTML  

    Floating point (F.P.) addition is a core operation for a wide range of applications. This brief presents an area-efficient, dynamically configurable, multiprecision architecture for F.P. addition. We propose an architecture of a double precision (DP) adder, which also supports a dual (two parallel) single precision (SP) computational feature. Key components involved in the F.P. adder architecture,... View full abstract»

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  • Accurate Fixed-Point Logarithmic Converter

    Publication Year: 2014 , Page(s): 526 - 530
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (791 KB) |  | HTML iconHTML  

    The hardware computation of the logarithm function is required in several applications, ranging from signal and image processing to telecommunication systems. This brief shows that most of previous proposed logarithmic converters, based on piecewise linear approximations, suffer from large errors when dealing with fixed-point input values with many fractional bits, a situation often encountered in... View full abstract»

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  • Energy Efficient MIMO Relay Transmissions via Joint Power Allocations

    Publication Year: 2014 , Page(s): 531 - 535
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    The energy efficient joint source-relay power allocation problem is studied for the multi-input multi-output (MIMO) amplify-and-forward two-hop relaying system, in which the objective of the optimization is the number of the bits per second per hertz per Joule with the guarantee of the minimum spectral efficiency (SE). By assuming perfect channel state information at the transmitter, the MIMO chan... View full abstract»

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  • Set-Membership NLMS Algorithm With Robust Error Bound

    Publication Year: 2014 , Page(s): 536 - 540
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (855 KB) |  | HTML iconHTML  

    A new robust error bound for the set-membership normalized least mean square (SMNLMS-REB) is proposed in this brief. The new robust set-membership error bound leads to improved robustness against impulsive noise and steady-state misalignment relative to those achieved in the set-membership normalized least mean square (SMNLMS) algorithm. Stability analysis shows that the proposed algorithm is stab... View full abstract»

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  • Pinning Controllability Analysis of Complex Networks With a Distributed Event-Triggered Mechanism

    Publication Year: 2014 , Page(s): 541 - 545
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (739 KB) |  | HTML iconHTML  

    Pinning control synchronization of complex networks is a fascinating and hot issue in the field of nonlinear science. However, the existing works are all based on a continuous-time feedback control strategy and assume that each network node can have continuous access to the states of its neighbors. This brief presents a novel distributed event-triggered mechanism for pinning control synchronizatio... View full abstract»

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  • IEEE xplore digital library

    Publication Year: 2014 , Page(s): 546
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  • 2014 IEEE membership application

    Publication Year: 2014 , Page(s): 547 - 548
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2014 , Page(s): C3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

    Publication Year: 2014 , Page(s): C4
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope