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Computers & Digital Techniques, IET

Issue 4 • Date July 2014

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Displaying Results 1 - 4 of 4
  • High-throughput dilution engine for sample preparation on digital microfluidic biochips

    Page(s): 163 - 171
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (900 KB)  

    The new generation of digital microfluidic biochips is capable of implementing complex biochemical laboratory assays (bioprotocols) on a tiny device for automatic and reliable analysis of fluid samples. Dilution of a sample fluid is one of the basic steps required in almost all bioprotocols. The authors design a dilution engine for sample preparation that can produce a stream of target droplets with a desired concentration factor by reusing the waste droplets. Also, a scheduling scheme is presented for mapping the dilution steps into the dilution engine. Next, an architecture is proposed to implement the dilution engine using only one (1:1) mix-split microfluidic module (mixer). The authors consider two schemes: (i) the base approach, where no on-chip storage unit (additional electrode) is available, and (ii) when a constant number of storage units is provided. Simulation results show that the second scheme saves the expensive reactants most efficiently, produces a stream of target droplets very fast and is highly suitable for supplying the required number of droplets as needed. View full abstract»

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  • Challenges and advances in Toffoli network optimisation

    Page(s): 172 - 177
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (191 KB)  

    This study gives a brief overview of the current trends in reversible logic synthesis with emphasis on template matching. The basic building block for reversible circuits considered here is the multiple-control Toffoli gate. Some approaches to synthesis are reviewed and the challenges are explained. Since many practical functions are not reversible, they must be embedded into reversible ones, if they are to be implemented using reversible logic. The complexity of such embeddings is expounded. A two phase synthesis is described where particular attention is devoted to the optimisation phase via template matching. Insights into the properties of the templates, have led to algorithms that aid the generation of templates. Until recently, the application of templates has been guided by different heuristics. A review of an exact template matching algorithm with a discussion of the implications of such an algorithm is given. Exact matching affects both the generation as well as the application of templates. Results from a prototype implementation are encouraging. View full abstract»

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  • Run-time power and performance scaling in 28 nm FPGAs

    Page(s): 178 - 186
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (978 KB)  

    The ability of scaling power and performance at run-time enables the creation of computing systems in which energy is consumed in proportion of the work to be done and the time available to do it. These systems favour active energy-efficient states in which useful computation is performed at low energy instead of using inactive energy savings modes that incur large latency and energy penalties to enter and exit modes in which the system is halted. This is particular useful in servers that spend most of their time at around 30% utilisation and are rarely fully idle or at maximum utilisation. A feature of an energy proportional computing system is that it must exhibit a wide dynamic range with multiple levels of energy and performance available. In this context, this study investigates how these levels can be obtained in commercially available state-of-the-art 28 nm field-programmable gate arrays (FPGAs) and characterises its benefits. Adaptive voltage and frequency scaling is employed to deliver proportional performance and power in these FPGA devices. The results reveal that the available voltage and frequency margins create a large number of performance and energy states with scaling possible at run-time with low overheads. Power savings of up to 64.98% are possible maintaining the original performance at a lower voltage. View full abstract»

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  • Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays

    Page(s): 187 - 197
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    Floating-point (FP) multiply-add fused (F1*F2±F3) and multiply-accumulate represent the most common arithmetic operation in a wide range of applications, such as graphic processing, multimedia or FP digital signal processing (DSP). This study proposes FP multiply-add fused units for low-precision formats (IEEE 16-bit half precision or the 32-bit single precision) which rely on modern Field Programmable Gate Array (FPGA) features such as the available integer multiply-accumulate-based support built-in the FPGA DSP blocks. These are employed as building-blocks within the mantissa data-path processing for the multiplication and the add/subtract operations. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on the addend, and, a right shift for one of the multiplicands. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are obtained for the multiply-add fused operation. View full abstract»

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IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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