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IEEE Transactions on Computers

Issue 6 • Date Jun 1993

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Displaying Results 1 - 17 of 17
  • One-bit delay in ring networks

    Publication Year: 1993, Page(s):735 - 737
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    In local area networks (LANs) with ring topologies, it is important to have minimum delay at the stations. It is explained why one-bit delay is the minimum possible delay at each station. It is shown that the stations delay depends on the medium access control (MAC) protocol executed in the ring. As an example, a recently published MAC protocol for rings is considered. It is explained why this pro... View full abstract»

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  • Reliability, reconfiguration, and spare allocation issues in binary-tree architectures based on multiple-level redundancy

    Publication Year: 1993, Page(s):713 - 723
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (892 KB)

    The locally redundant modular tree (LRMT) schemes offer high yield and reliability for trees of relatively few levels but are less effective for large binary trees due to the imbalance of reliability of different levels. A new multiple-level redundancy tree (MLRT) architecture that combines modular schemes with level-oriented schemes which lead to better yield and reliability is presented. The MLR... View full abstract»

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  • Response to `one-bit delay in ring networks' by R. Cohen

    Publication Year: 1993, Page(s):737 - 738
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    The authors respond to section III of the above-titled work (ibid., vol.42, no.6, pp.735-737, June 1993), in which it is shown that their medium access control (MAC) protocol for rings (bid., vol.39, no.3, pp.289-299, Mar. 1990) cannot be implemented with minimum delay. They point out some differences in terminology and provide further clarification of their work View full abstract»

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  • A unified negative-binomial distribution for yield analysis of defect-tolerant circuits

    Publication Year: 1993, Page(s):724 - 734
    Cited by:  Papers (62)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    It has been recognized that the yield of fault-tolerant VLSI circuits depends on the size of the fault clusters. Consequently, models for yield analysis have been proposed for large-area clustering and small-area clustering, based on the two-parameter negative-binomial distribution. The addition of a new parameter, the block size, to the two existing parameters of the fault distribution is propose... View full abstract»

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  • Concurrent error detection on programmable systolic arrays

    Publication Year: 1993, Page(s):752 - 756
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    Two concurrent error detection (CED) methods are presented. The methods, skewed replicated computation streams and interleaved replicated computation streams, are both well-suited for shared register and other systolic arrays. They allow software tradeoffs between time- and space-multiplexing with no special hardware. The methods can be automatically applied to any systolic program View full abstract»

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  • On asymmetric invalidation with partial tests

    Publication Year: 1993, Page(s):764 - 768
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    R. Gupta and I.V. Ramakrishnan (1987) proposed a general model for fault diagnosis that uniformly handles intermittent faults, masking, and partial testing. In this model, the diagnosability problem is open if asymmetric invalidation is used, although a polynomial time algorithm was once incorrectly claimed. It is shown that the problem is really co-NP complete. An efficient diagnosis algorithm fo... View full abstract»

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  • The performance of parity placements in disk arrays

    Publication Year: 1993, Page(s):651 - 664
    Cited by:  Papers (27)  |  Patents (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1092 KB)

    Due to recent advances in central processing unit (CPU) and memory system performance, input/output (I/O) systems are increasingly limiting the performance of modern computer systems. Redundant arrays of inexpensive disks (RAID) have been proposed to meet the impending I/O crisis. RAIDs substitute many small inexpensive disks for a few large expensive disks to provide higher performance, smaller f... View full abstract»

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  • Parametric module allocation on partial k-trees

    Publication Year: 1993, Page(s):738 - 742
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The problem of allocating modules to processors in a distributed system to minimize total costs when the underlying communication graph is a partial k-tree and all costs are linear functions of a real parameter t is considered. It is shown that if the number of processors is fixed, the sequence of optimum assignments that are obtained as t varies from zero to infinity ca... View full abstract»

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  • Accumulator-based compaction of test responses

    Publication Year: 1993, Page(s):643 - 650
    Cited by:  Papers (49)  |  Patents (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is introduced. The asymptotic and transient coverage drop introduced by accumulators with binary and 1's complement adders is studied using Markov chain models. It is proven that the asymptotic coverage drop in ABC with binary adders is 2-k, where k is the number of bits in the adder that the... View full abstract»

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  • The cost of broadcasting on star graphs and k-ary hypercubes

    Publication Year: 1993, Page(s):756 - 759
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    It is shown that for two common broadcasting problems, a star graph performs better than a k-ary hypercube with a comparable number of nodes only in networks consisting of an impractically large numbers of nodes. This result is based on a comparison of the costs of known solutions to the one-to-all broadcast and the complete broadcast problems for each network. It is suggested that the co... View full abstract»

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  • A new class of optimal bounded-degree VLSI sorting networks

    Publication Year: 1993, Page(s):746 - 752
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    Minimum-area very large scale integration (VLSI) networks have been proposed for sorting N elements in O(log,N ) time. However, most of such networks proposed have complex structures, and no explicit network construction is given in others. New designs of optimal VLSI sorters that combine rotate-sort with enumeration-sort to sort N numbers, each of length ... View full abstract»

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  • Parallel computations on reconfigurable meshes

    Publication Year: 1993, Page(s):678 - 692
    Cited by:  Papers (93)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1504 KB)

    The mesh with reconfigurable bus is presented as a model of computation. The reconfigurable mesh captures salient features from a variety of sources, including the CAAPP, CHiP, polymorphic-torus network, and bus automation. It consists of an array of processors interconnected by a reconfigurable bus system that can be used to dynamically obtain various interconnection patterns between the processo... View full abstract»

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  • A systematic approach for mapping application tasks in hypercubes

    Publication Year: 1993, Page(s):742 - 746
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    A systematic approach for mapping application tasks to hypercubes is proposed. This method is based on a partitioning algorithm in which the final mapping is rendered as a task-node tuple assignment for an n-cube system. For this method, a single-tasking environment in which each task is assigned to a unique processor is assumed. Dilation-bound and expansion-ratio parameters are used to e... View full abstract»

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  • Isomorphism of conflict graphs in multistage interconnection networks and its application to optimal routing

    Publication Year: 1993, Page(s):665 - 677
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB)

    A study on the isomorphism of conflict graphs in multistage interconnection networks (MINs) and its applications is outlined. A concept called group-transformation is introduced for the baseline network, which induces an equivalence partition on the set of all permutations. All members belonging to the same equivalence class have isomorphic conflict graphs. Thus, determination of conflict resoluti... View full abstract»

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  • Designing optimum one-level carry-skip adders

    Publication Year: 1993, Page(s):759 - 764
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    The author shows how to design one-level carry-skip adders that attain very high speeds. One-level carry-skip adders are very fast adders that are hardly more complex than the much-slower ripple adders. The design procedure allows the use of realistic component delays obtained by simulation and is technology-independent. An example of a 64-b, 1 μm CMOS adder is given. This adder achieves an add... View full abstract»

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  • Hardware implementation of Montgomery's modular multiplication algorithm

    Publication Year: 1993, Page(s):693 - 699
    Cited by:  Papers (110)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic View full abstract»

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  • The minimal test set for multioutput threshold circuits implemented as sorting networks

    Publication Year: 1993, Page(s):700 - 712
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (984 KB)

    It is shown that an n-input sorting network (SN) can be used to implement an n-variable symmetric threshold functions using the least amount of hardware. An algorithm to derive Boolean functions implemented on any line of any n-input threshold circuit Tn implemented as a SN is given. A heuristic procedure for generating the minimal test set for any threshold c... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org