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Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 7 • Date July 2014

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Displaying Results 1 - 25 of 27
  • Front Cover

    Page(s): C1
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  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Page(s): C2
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  • Table of contents

    Page(s): 1117 - 1118
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  • Laser-Sintered Silver Nanoparticles as a Die Adhesive Layer for High-Power Light-Emitting Diodes

    Page(s): 1119 - 1124
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    A laser-sintered die adhesive based on silver nanoparticles (AgNPs) is used to fabricate high-power light-emitting diodes (LEDs). Following the optimization of the laser power and the irradiation time, the laser sintering of AgNPs without any organic binder shows the comparable adhesion property to that of conventional LED chip bonding layer with silicone and silver-loaded epoxy adhesives. Among tested LEDs, devices using the laser-sintered AgNP adhesive exhibit the best performance in both light-emitting efficiency and reliability, which are governed by the thermal conducting property of chip bonder. Morphological analyses indicate that the elongated microstructure of AgNP-adhesive layer by laser-sintering process contributes to the performance enhancement of LEDs. View full abstract»

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  • High Refractive Index and Transparent Nanocomposites as Encapsulant for High Brightness LED Packaging

    Page(s): 1125 - 1130
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    A high refractive index (RI) and transparent encapsulant material is in great demand for light emitting diode (LED) packaging to lower the RI contrasts between a LED chip and an encapsulant, and therefore improve the light extraction efficiency. In this paper, we prepared TiO2/silicone nanocomposites and studied the effects of the crystalline phases of TiO2, and the TiO2 surface modifications on their optical properties. The rutile TiO2 was found to be more effective to increase the RI of the nanocomposite than the anatase phase TiO2. At a 5 wt.% loading of TiO2, the RI was as high as 1.62 at the wavelength of 589 nm, which represents a significant improvement from 1.54 for silicone resin. In addition, surface modification was carried out using vinyl-terminated silane to improve the dispersion of nanoparticles in a silicone matrix, leading to a high relative transmittance of 84%. We also demonstrated that the optical property degradation of the nanocomposites in this paper was negligible after the accelerated reliability test. View full abstract»

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  • Separation Characteristics of an LMPA-Polymer Mixture for the Encapsulation of Organic Light-Emitting Diode

    Page(s): 1131 - 1135
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    An encapsulation method using the separation of low melting point alloy (LMPA) and a polymer from an LMPA-polymer mixture is proposed. Sn-Bi alloy and epoxy were used for the mixture. Separation was conducted using a two-step heat treatment of 160 °C for 5 min and 180 °C for 5 min. We found that the flux contained in the Sn-Bi solder played an important role in the separation process. A Cu sacrificial layer was introduced using the sputtering method under the Sn-Bi layer with thickness variations of 1500, 3000, and 6000 Å. Using the 6000-Å-thick Cu layer, the LMPA formed a well-separated and continuous sealing line. This double-line structure shows good potential for use as a sealing line for organic light-emitting diode encapsulation. View full abstract»

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  • LIM2X: Generating X-Parameters in the Time Domain Using the Latency Insertion Method

    Page(s): 1136 - 1143
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    X-parameters, a formalism for describing the nonlinear relationship between power waves, has been shown to have a wide array of applications in the modeling of nonlinear devices and systems. In this paper, the polyharmonic distortion model and the latency insertion method (LIM) are combined to generate X-parameters from a time-domain simulation. This technique leverages the speed and convergence advantages of LIM to generate X-parameters, which are defined in the frequency domain. Both small- and large-signal X-parameter results are compared with those generated using harmonic balance. View full abstract»

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  • Warpage Behavior and Life Prediction of a Chip-on-Flex Package Under a Thermal Cycling Condition

    Page(s): 1144 - 1151
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    Flip-chip assembly has been widely adapted to various electronic devices due to advantages, such as miniaturization of electronic devices and high density integration. The chip-on-flex (COF) package used in this paper is a flip-chip package with an anisotropic conductive adhesive flim (ACF) interconnection and shows flexible features and reduced thickness compared with chip-on-board (COB) packages. All electronic packages experience temperature variation during service conditions and under environmental changes. Under temperature variation, stresses emerge due to the differences in the coefficient of thermal expansion among components. In order to evaluate the thermomechanical reliability of a COF package, a thermal cycling (TC) test was conducted. A moiré experiment using Twyman/Green interferometry was performed to observe the warpage behavior of the package under a TC condition. Through the experiment, the rate of change of chip warpage with respect to temperature (dw/dT) as a parameter of the thermal damage model was obtained. A finite element analysis (FEA) was also performed to calculate the maximum shear stress at the ACF layer as another parameter of the model. From the experiment and FEA results, the thermal damage model can accurately represent the TC life of the COF package. However, based on observations of different warpage behavior of the COF package compared with a COB package from the moiré experiment, a modified thermal damage model that can predict the TC life of both packages more accurately was proposed. View full abstract»

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  • Evaluation of Die Strength by Using Finite Element Method With Experiment Validation

    Page(s): 1152 - 1158
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    3-D chip stacking packaging is becoming increasingly popular in the electronics packaging industry because the demand of current market has focused on cheaper products with higher performance characteristics and smaller form factors. Silicon wafers must be ground using wafer-thinning processes to achieve smaller packaging sizes. However, cracks may form in the silicon chips during stacking or while the device is in use. In this paper, the ball-breaker test is used to determine the maximum allowable force on a (1 0 0) silicon die. Finite element (FE) analysis using the commercial software ANSYS/LS-DYNA3-D is introduced to calculate the strength of the silicon die and compared with the experimental findings shows that the results are consistent with Hertzian contact theory. The effects of silicon die thickness and foundation material on the silicon die strength are also discussed in this paper. As the applied force increases, a crack appears on the edge of the contact area and propagates within the die. A decrease in die thickness results in the formation of radial cracks on the bottom surface as well as significant bending effects on the test die. The initial failure may originate from the radial crack and propagate toward the top surface of the die leading to die breakage. The strengths determined in this experiment decrease as the test die becomes thinner. Furthermore, if the insignificant bending behavior is observed, simulation results show that the maximum allowable force on a silicon die increases when a softer foundation material is used. However, a thin test die placed on a soft material is considerably easy to break because the tensile stress on the bottom surface of the die caused by the rapid increase in bending behavior significantly affects die breakage. View full abstract»

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  • Thermal Pathfinding for 3-D ICs

    Page(s): 1159 - 1168
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    System architects traditionally use high-level models of component blocks to predict trends for various design metrics. However, with continually increasing design complexity and a confusing array of manufacturing choices, system-level design decisions cannot be made without considering physical-level details. This effect is more pronounced for 3-D integrated circuits (ICs) because it provides a plethora of physical-level design choices, such as the number of stacking layers and the type of 3-D bonding method, along with the choices provided by 2-D ICs. Thus, it is necessary for system-level flows to predict the complex interactions among system performance, power, temperature, floorplanning, process technology, computer architecture, and software/workloads. This is often called pathfinding. This paper presents a pathfinding flow that integrates SystemC transaction-level electrical and dynamic thermal simulations. The goal of this flow is to pass complex physical constraints to system architects in a convenient form. The applicability of the proposed flow is shown using an example stacking of two processor cores and L2 cache in two-tier 3-D stack. View full abstract»

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  • Insulation Resistance and Leakage Currents in Low-Voltage Ceramic Capacitors With Cracks

    Page(s): 1169 - 1176
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    Measurement of insulation resistance (IR) in multilayer ceramic capacitors (MLCCs) is considered a screening technique that ensures the dielectric is defect-free. This paper analyzes the effectiveness of this technique for revealing cracks in ceramic capacitors. It is shown that absorption currents prevail over the intrinsic leakage currents during standard IR measurements at room temperature. Absorption currents, and consequently IR, have a weak temperature dependence, increase linearly with voltage (before saturation), and are not sensitive to the presence of mechanical defects. On the contrary, intrinsic leakage currents increase super-linearly with voltage and exponentially with temperature (activation energy is in the range from 0.6 to 1.1 eV). Leakage currents associated with the presence of cracks have a weaker dependence on temperature and voltage compared with the intrinsic leakage currents. For this reason, intrinsic leakage currents prevail at high temperatures and voltages, thus masking the presence of defects. View full abstract»

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  • Analysis of the Interruption Process of Selective Miniature Circuit Breaker With Permanent Magnet Release

    Page(s): 1177 - 1183
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    The interruption process of the new-type selective miniature circuit breaker (SMCB) is different from the traditional low-voltage circuit breaker (LVCB). According to the operating principle of the SMCB, its interruption process can be divided into three stages; the corresponding mathematical model and calculation method are proposed as well. The calculation of the static characteristic of the magnetic release equipped with the permanent magnet shows that the influence of the current direction on the electromagnetic force cannot be ignored, which lead to the minimum tripping current of the release is equal to -315 and 490 A, respectively, when the armature is close to the permanent magnet. With the simulation and experimental results when the effective value of the prospective short-circuit current is 644 A and 1.5 kA, it indicates that the bigger the closing phase angle is, the quicker the arc ignition between the main contacts and the less arcing time will be. Moreover, the typical interruption parameters of the simulation and experimental results are comparable, and it demonstrates that the proposed method can be used for the optimization design of the SMCB. View full abstract»

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  • Signal-Integrity Optimization for Complicated Multiple-Input Multiple-Output Networks Based on Data Mining of S-Parameters

    Page(s): 1184 - 1192
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    In this paper, an efficient signal-integrity analysis and optimization method for complicated multiple-input multiple-output (MIMO) networks is proposed, in which data mining is applied to discover the concealed information in black-box S-parameter models. Instead of performing a number of circuit simulations, data mining employs mathematical search algorithm directly into the model, which can save significant analyzed time and improve the efficiency. An optimized mining flow is presented for large scale data set, where the data processing and data mining are performed simultaneously, and thus it is unnecessary to save large extracted data. The proposed data mining method consider both the interconnect structure and the stimulated pattern of a MIMO system, which can perform thoughtful analysis and optimization with high efficiency. Two examples, signal-integrity analysis of two coupled microstrip lines and noise coupling among multiple signal vias through a power-ground plane pair, are presented to demonstrate the efficiency of the proposed data mining method in signal-integrity optimization design. View full abstract»

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  • 5-Gb/s and 10-GHz Center-Frequency Gaussian Monocycle Pulse Transmission Using 65-nm Logic CMOS With On-Chip Dipole Antenna and High- $kappa $ Interposer

    Page(s): 1193 - 1200
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    Interchip data transmission was demonstrated using impulse radio ultrawideband complementary metal- oxide-semiconductor (CMOS) transmitter integrate circuits with on-chip dipole antennas. A differential pseudorandom binary sequence of 27 data of Gaussian monocycle pulse (GMP) was formed by 65-nm CMOS logic circuits using upand downpulses with certain gate delays. The CMOS transmitter generated 5-Gb/s GMP with the center frequency of 10 GHz. To improve transmission gains, an interposer with the high dielectric constant (εr = 38) and optimized thickness was inserted under the CMOS chips as a dielectric slab waveguide. 2-Gb/s GMP signals were transmitted and received in the distance of 10 mm by use of the CMOS on-chip antennas and the high-κ interposer. View full abstract»

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  • Parallel Simulation of Large Linear Circuits With Nonlinear Terminations Using High-Order Stable Methods

    Page(s): 1201 - 1211
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    To meet the growing demand for efficient circuit simulation tools, Obreshkov formula (ObF)-based high-order integration methods were recently proposed. However, one of the challenges in this method is the growing computational cost of the solution at a particular time point with the increasing orders of the ObF. To address this issue and target high-speed circuits with large linear blocks and nonlinear loads, a new parallel framework is proposed in this paper to minimize the CPU time associated with the solution at any time point. For this purpose, recently identified special properties of the resulting circuit matrices and the node-tearing principles are exploited, while developing an efficient parallel simulation framework. Numerical examples are presented to demonstrate the validity and efficiency of the proposed parallel method. View full abstract»

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  • Using Via Stubs in Periodic Structures for Microwave Filter Design

    Page(s): 1212 - 1221
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    This paper presents a novel form of microwave filter construction using vias (plated through holes) available in generic printed circuit boards as the main building block. It is demonstrated that for a certain arrangement of vias, the resonant behavior of via stubs can be used to create a low- or a high-pass filter using open- or short-circuited vias, respectively. These stubs are periodically cascaded, resembling an analogous implementation using transmission-line stub filters. It will be shown that such a via filter structure can achieve insertion loss lower than 0.1 dB and return loss of about -60 dB in the passband at GHz frequencies. Measurements, full-wave, and physics-based simulations are presented to verify this novel filter concept and to provide design guidelines in the frequency range from 1 to 20 GHz. View full abstract»

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  • Design of Wide Passband Microstrip Branch-Line Couplers With Multiple Sections

    Page(s): 1222 - 1227
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    Novel design equations are proposed for the 3-dB microstrip branch-line coupler with a wide passband, utilizing multisectional branch lines. In addition, the proposed method makes it possible to reduce the internal impedance levels of branch-line couplers so they may be physically constructed by microstrip lines. Further, in terms of measured results, there is a wide bandwidth >70%. Synthesis of the 3-dB branch-line coupler is described in details as well. Good agreement between theoretical calculation and measurement validates the proposed method. View full abstract»

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  • Inkjet Printed Series-Fed Two-Dipole Antenna Comprising a Balun Filter on Liquid Crystal Polymer Substrate

    Page(s): 1228 - 1236
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    This paper presents a series-fed two-dipole antenna, fabricated on a liquid crystal polymer (LCP) substrate using inkjet-printing technology. The radio frequency characteristics of inkjet-printing silver film onto an LCP substrate are studied using the microstrip line. The proposed antenna consists of two modified dipole elements of distinct lengths: a modified ground plane and a balun filter yielding a wide bandwidth with bandpass responses. The proposed antenna can be used at frequency band of 26-33 GHz. The bending behaviors of the microstrip line and antenna are also measured. Inkjet printing on LCP substrates provides a low-cost, compact, and flexible packaging solution that can be used in future communication technology. View full abstract»

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  • Low Loss Suspended Membrane on Low Resistivity Silicon and Its Applications to Millimetre-Wave Passive Circuits

    Page(s): 1237 - 1244
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    This paper presents the fabrication process of a thin suspended membrane on normal low resistivity silicon (LRSi), which is then utilized to design millimeter-wave (mm-wave) transmission line and passive circuits with low loss. First, two redistribution metal layers are formed on a plain LRSi wafer with benzocyclobutene in-between. Then, the wafer is thinned down and etched from backside with a specific pattern. Based on this process, a volume is introduced underneath the front side structure and the lossy LRSi substrate is replaced by air, which is the ideal substrate with no loss. Using this method, the substrate loss that contributes the majority part of total loss in mm-wave circuits on LRSi is eliminated. As the operating frequency goes into mm-wave region, the circuit size is scaled down so that the suspended portion is so small that it will not increase the mechanical instability of the structure. Therefore, the proposed suspended membrane on LRSi technology provides an excellent platform to construct mm-wave components. A U-shaped slotline resonator formed on the first redistribution layer is proposed and its quality factors are studied in detail. A second-order bandpass filter is designed and implemented by cascading two such U-shape slotline resonators. The measured frequency responses exhibit good filtering performance, with fractional bandwidth of 13.9% at 126.8 GHz, midband insertion loss of 3.9 dB and passband return loss larger than 14.2 dB. It demonstrates that the proposed suspended membrane on LRSi technology is an excellent candidate for designing low loss mm-wave components. View full abstract»

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  • Void Detection in TSVs With X-Ray Image Multithreshold Segmentation and Artificial Neural Networks

    Page(s): 1245 - 1250
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    Through-silicon via (TSV) is a vertical channel that passes through a chip to connect stacked dies in 3-D packaging. Void may be produced during the high aspect ratio TSV filling process with copper electroplating method. Therefore, void detection becomes an important aspect for high-quality TSV devices. In this paper, a rapid void detection method using a single 2-D X-ray imaging was developed. An image processing method was used to divide the X-ray image into some small blocks for multithreshold image cutting and feature extraction. An artificial neural network was then used to find and locate the blocks that contain voids. The effects of segmentation threshold, various block widths, and heights were studied; a block size of 30 × 40 pixels (width × height) is recommended. The void detection is more sensitive to block width than height. Experiments show that the method proposed in this paper can automatically and rapidly detect voids in TSVs using one 2-D X-ray image. View full abstract»

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  • Endpoint Detection in Low Open Area TSV Fabrication Using Optical Emission Spectroscopy

    Page(s): 1251 - 1260
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    Through-silicon via (TSV) technology is a key enabler for 3-D and 2.5-D integration, which provides low-power and high-bandwidth chip-to-chip communication. During TSV fabrication, over-etching may cause notching at the base of the TSVs, resulting in TSV diameter variations. Endpoint detection (EPD) techniques are critical for controlling TSV diameter, and detecting the endpoint for low open areas presents a serious challenge to process engineers. In this paper, a hybrid partial least squares-support vector machine model for optical emission spectroscopy data are successfully demonstrated for an EPD of low open area TSVs. Accurate EPD results are shown for 120, 80, and 25 (mu) m diameter TSVs. View full abstract»

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  • [Blank page - back cover]

    Page(s): 1261 - 1262
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  • Open Access

    Page(s): 1263
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  • IEEE Xplore Digital Library

    Page(s): 1264
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  • Together, we are advancing technology

    Page(s): 1265
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Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

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Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University