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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • Date July 2014

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Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2014, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2014, Page(s): C2
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  • Multiple-Population Moment Estimation: Exploiting Interpopulation Correlation for Efficient Moment Estimation in Analog/Mixed-Signal Validation

    Publication Year: 2014, Page(s):961 - 974
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (11571 KB) | HTML iconHTML

    Moment estimation is an important problem during circuit validation, in both presilicon and postsilicon stages. From the estimated moments, the probability of failure and parametric yield can be estimated at each circuit configuration and corner, and these metrics are used for design optimization and making product qualification decisions. The problem is especially difficult if only a very small s... View full abstract»

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  • Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications

    Publication Year: 2014, Page(s):975 - 988
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2531 KB) | HTML iconHTML

    Programmable reversible logic is emerging as a prospective logic design style for implementation in low power, low frequency applications where minimal impact on circuit heat generation is desirable, such as mitigation of differential power analysis attacks. Adiabatic logic is an implementation of reversible logic in CMOS where the current flow through the circuit is controlled such that the energ... View full abstract»

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  • A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)

    Publication Year: 2014, Page(s):989 - 1002
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (14301 KB) | HTML iconHTML

    In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is proposed to reduce the number of completion detection (CD) circuits while retaining the required QDI... View full abstract»

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  • Four-Valued Reasoning and Cyclic Circuits

    Publication Year: 2014, Page(s):1003 - 1016
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5891 KB) | HTML iconHTML

    Allowing cycles in a logic circuit can be advantageous, for example, by reducing the number of gates required to implement a given Boolean function, or a set of functions. However, a cyclic circuit may easily be ill behaved. For instance, it may have some output wire oscillation instead of reaching a steady state. Propositional three-valued logic has long been used in tests for good behavior of cy... View full abstract»

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  • Accelerated Harmonic-Balance Analysis Using a Graphical Processing Unit Platform

    Publication Year: 2014, Page(s):1017 - 1030
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8341 KB) | HTML iconHTML

    This paper describes a new approach to accelerate the simulation of the steady-state response of nonlinear circuits using the harmonic-balance (HB) technique. The approach presented in this paper focuses on the direct factorization of the Jacobian matrix, of the HB nonlinear equations, using a graphical processing unit (GPU) platform. The computational core of the proposed approach is based on dev... View full abstract»

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  • Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC

    Publication Year: 2014, Page(s):1031 - 1042
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (13633 KB) | HTML iconHTML

    With no further shrinking of device size, 3-D chip stacking by through-silicon-via (TSV) has been identified as an effective way to achieve better performance in speed and power. However, such solution inevitably encounters challenges in thermal dissipation since stacked dies generate a significant amount of heat per unit volume. We leverage an integrated design methodology of stacked-signal-TSVs ... View full abstract»

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  • Learning-Based Power Management for Multicore Processors via Idle Period Manipulation

    Publication Year: 2014, Page(s):1043 - 1055
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (14324 KB) | HTML iconHTML

    Learning-based dynamic power management (DPM) techniques, being able to adapt to varying system conditions and workloads, have attracted a lot of research attention recently. To the best of our knowledge, however, none of the existing learning-based DPM solutions are dedicated to power reduction in multicore processors, although they can be utilized by treating each processor core as a standalone ... View full abstract»

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  • A Variability-Aware Adaptive Test Flow for Test Quality Improvement

    Publication Year: 2014, Page(s):1056 - 1066
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9797 KB) | HTML iconHTML

    In this paper, we propose a process-variability-aware adaptive test flow that realizes efficient and comprehensive detection of parametric faults. A parametric fault is essentially a malfunction in a large-scale integration chip, which is caused by the variability in fabrication processes. In our adaptive test framework, test pattern sets are altered on individual chips in order to apply the optim... View full abstract»

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  • Test-Delivery Optimization in Manycore SOCs

    Publication Year: 2014, Page(s):1067 - 1080
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (11326 KB) | HTML iconHTML

    We present two test-data delivery optimization algorithms for system-on-chip (SoC) designs with hundreds of cores, where a network-on-chip (NoC) is used as the interconnection fabric. We first present an effective algorithm based on a subset-sum formulation to solve the test-delivery problem in NOCs with arbitrary topology that use dedicated routing. We further propose an algorithm for the importa... View full abstract»

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  • A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug

    Publication Year: 2014, Page(s):1081 - 1094
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8846 KB) | HTML iconHTML

    A major challenge in post-silicon debug is the lack of observability to the internal signals of a chip. Trace buffer technology provides one venue to address this challenge by online tracing of a few selected state elements. Due to the limited bandwidth of the trace buffer, only a few state elements can be selected for tracing. Recent research has focused on automated trace signal selection proble... View full abstract»

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  • Selection of Functional Test Sequences With Overlaps

    Publication Year: 2014, Page(s):1095 - 1099
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3616 KB) | HTML iconHTML

    Functional test sequences may be generated for simulation-based design verification, and used as manufacturing tests or for speed binning. A class of earlier procedures selects functional test sequences for target faults from a set of available sequences in order to reduce the storage requirements and test application time. This paper describes a procedure that reduces the storage requirements fur... View full abstract»

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  • A Global Maximum Error Controller-Based Method for Linearization Point Selection in Trajectory Piecewise-Linear Model Order Reduction

    Publication Year: 2014, Page(s):1100 - 1104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6635 KB) | HTML iconHTML

    We propose a new linearization point selection method based on a global maximum error controller for the trajectory piecewise-linear (TPWL) model order reduction (MOR). This method is based on a simple fact that the simulation cost of the TPWL model is very low, and selects the state at which the responses of the current TPWL model and the full nonlinear model have the maximum difference as a new ... View full abstract»

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  • Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm

    Publication Year: 2014, Page(s):1105 - 1109
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1716 KB) | HTML iconHTML

    The secure hash algorithm (SHA)-3 has been selected in 2012 and will be used to provide security to any application which requires hashing, pseudo-random number generation, and integrity checking. This algorithm has been selected based on various benchmarks such as security, performance, and complexity. In this paper, in order to provide reliable architectures for this algorithm, an efficient conc... View full abstract»

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  • Adaptive Paired Page Prebackup Scheme for MLC NAND Flash Memory

    Publication Year: 2014, Page(s):1110 - 1114
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3186 KB) | HTML iconHTML

    Multilevel cell (MLC) NAND flash memory is more cost effective compared with single-level cell NAND flash memory as it can store two or more bits in a memory cell. However, in MLC flash memory, a programming operation can corrupt the paired page under abnormal termination. In order to solve the paired page problem, a backup scheme is generally used, which inevitably causes performance degradation ... View full abstract»

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  • Open Access

    Publication Year: 2014, Page(s): 1115
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  • Together, we are advancing technology

    Publication Year: 2014, Page(s): 1116
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2014, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2014, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu