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Emerging Topics in Computing, IEEE Transactions on This IEEE Publication is an Open Access only journal. Open Access provides unrestricted online access to peer-reviewed journal articles.

Issue 1 • Date March 2014

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Displaying Results 1 - 11 of 11
  • [Front cover]

    Page(s): C1
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    Freely Available from IEEE
  • IEEE Transactions on Emerging Topics in Computing publication information

    Page(s): C2
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  • Table of contents

    Page(s): 1
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  • Special Issue on Emerging Nanoscale Architectures for Hardware Security, Trust, and Reliability: Part 1

    Page(s): 2 - 3
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  • On-Chip Nanoscale Capacitor Decoupling Architectures for Hardware Security

    Page(s): 4 - 15
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (11223 KB) |  | HTML iconHTML  

    This paper presents new power analysis attack (PAA) countermeasures for nanoscale cryptographic devices. Specifically, three circuit level architectures called partial decoupling architecture, full decoupling architecture, and randomized switch box architecture are developed and analyzed. The architectures' primary feature is the use of on-chip nMOS gate capacitors as intermediate power storage elements to decouple the power supply from internal low-power modules processing sensitive data. The proposed countermeasures are algorithm independent and allow different tradeoffs between security protection and the incurred overheads. Test benches of the proposed architectures were simulated in 65-nm TSMC CMOS technology. A correlation PAA was performed for each test bench targeting a custom implementation of the advanced encryption standard subbytes operation. All architectures were found to resist the correlation PAA at the power supply, with the more complex architectures also offering protection against invasive attacks. The success value indicator was used to analyze the effectiveness of the countermeasures. It was found that all architectures provided a negative value at the power supply, showing protection against PAAs. We demonstrate that the use of nMOS gate capacitors can help to increase security and present a feasibility analysis focused on the needed decoupling capacitances. View full abstract»

    Open Access
  • Processor-Based Strong Physical Unclonable Functions With Aging-Based Response Tuning

    Page(s): 16 - 29
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (27689 KB) |  | HTML iconHTML  

    A strong physically unclonable function (PUF) is a circuit structure that extracts an exponential number of unique chip signatures from a bounded number of circuit components. The strong PUF unique signatures can enable a variety of low-overhead security and intellectual property protection protocols applicable to several computing platforms. This paper proposes a novel lightweight (low overhead) strong PUF based on the timings of a classic processor architecture. A small amount of circuitry is added to the processor for on-the-fly extraction of the unique timing signatures. To achieve desirable strong PUF properties, we develop an algorithm that leverages intentional post-silicon aging to tune the inter- and intra-chip signatures variation. Our evaluation results show that the new PUF meets the desirable inter- and intra-chip strong PUF characteristics, whereas its overhead is much lower than the existing strong PUFs. For the processors implemented in 45 nm technology, the average inter-chip Hamming distance for 32-bit responses is increased by 16.1% after applying our post-silicon tuning method; the aging algorithm also decreases the average intra-chip Hamming distance by 98.1% (for 32-bit responses). View full abstract»

    Open Access
  • A PUF Based on a Transient Effect Ring Oscillator and Insensitive to Locking Phenomenon

    Page(s): 30 - 36
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (4632 KB) |  | HTML iconHTML  

    This paper presents a new silicon physical unclonable function (PUF) based on a transient effect ring oscillator (TERO). The proposed PUF has state of the art PUF characteristics with a good ratio of PUF response variability to response length. Unlike RO-PUF, it is not sensitive to the locking phenomenon, which challenges the use of ring oscillators for the design of both PUF and TRNG. The novel architecture using differential structures guarantees high stability of the TERO-PUF. The area of the TERO-PUF is relatively high, but is still comparable with other PUF designs. However, since the same piece of hardware can be used for both PUF and random number generation, the proposed principle offers an interesting low area mixed solution. View full abstract»

    Open Access
  • Robust and Reverse-Engineering Resilient PUF Authentication and Key-Exchange by Substring Matching

    Page(s): 37 - 49
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1123 KB) |  | HTML iconHTML  

    This paper proposes novel robust and low-overhead physical unclonable function (PUF) authentication and key exchange protocols that are resilient against reverse-engineering attacks. The protocols are executed between a party with access to a physical PUF (prover) and a trusted party who has access to the PUF compact model (verifier). The proposed protocols do not follow the classic paradigm of exposing the full PUF responses or a transformation of them. Instead, random subsets of the PUF response strings are sent to the verifier so the exact position of the subset is obfuscated for the third-party channel observers. Authentication of the responses at the verifier side is done by matching the substring to the available full response string; the index of the matching point is the actual obfuscated secret (or key) and not the response substring itself. We perform a thorough analysis of resiliency of the protocols against various adversarial acts, including machine learning and statistical attacks. The attack analysis guides us in tuning the parameters of the protocol for an efficient and secure implementation. The low overhead and practicality of the protocols are evaluated and confirmed by hardware implementation. View full abstract»

    Open Access
  • Test Versus Security: Past and Present

    Page(s): 50 - 62
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1832 KB) |  | HTML iconHTML  

    Cryptographic circuits need to be protected against side-channel attacks, which target their physical attributes while the cryptographic algorithm is in execution. There can be various side-channels, such as power, timing, electromagnetic radiation, fault response, and so on. One such important side-channel is the design-for-testability (DfT) infrastructure present for effective and timely testing of VLSI circuits. The attacker can extract secret information stored on the chip by scanning out test responses against some chosen plaintext inputs. The purpose of this paper is to first present a detailed survey on the state-of-the-art in scan-based side-channel attacks on symmetric and public-key cryptographic hardware implementations, both in the absence and presence of advanced DfT structures, such as test compression and X-masking, which may make the attack difficult. Then, the existing scan attack countermeasures are evaluated for determining their security against known scan attacks. In addition, JTAG vulnerability and security countermeasures are also analyzed as part of the external test interface. A comparative area-timing-security analysis of existing countermeasures at various abstraction levels is presented in order to help an embedded security designer make an informed choice for his intended application. View full abstract»

    Open Access
  • Reverse Engineering Digital Circuits Using Structural and Functional Analyses

    Page(s): 63 - 80
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    Integrated circuits (ICs) are now designed and fabricated in a globalized multivendor environment making them vulnerable to malicious design changes, the insertion of hardware Trojans/malware, and intellectual property (IP) theft. Algorithmic reverse engineering of digital circuits can mitigate these concerns by enabling analysts to detect malicious hardware, verify the integrity of ICs, and detect IP violations. In this paper, we present a set of algorithms for the reverse engineering of digital circuits starting from an unstructured netlist and resulting in a high-level netlist with components such as register files, counters, adders, and subtractors. Our techniques require no manual intervention and experiments show that they determine the functionality of >45% and up to 93% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375000 combinational elements. Our inference algorithms cover 68% of the gates in this SOC. We also demonstrate that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured netlist. View full abstract»

    Open Access
  • Fabrication Attacks: Zero-Overhead Malicious Modifications Enabling Modern Microprocessor Privilege Escalation

    Page(s): 81 - 93
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (11321 KB) |  | HTML iconHTML  

    The wide deployment of general purpose and embedded microprocessors has emphasized the need for defenses against cyber-attacks. Due to the globalized supply chain, however, there are several stages where a processor can be maliciously modified. The most promising stage, and the hardest during which to inject the hardware trojan, is the fabrication stage. As modern microprocessor chips are characterized by very dense, billion-transistor designs, such attacks must be very carefully crafted. In this paper, we demonstrate zero overhead malicious modifications on both high-performance and embedded microprocessors. These hardware trojans enable privilege escalation through execution of an instruction stream that excites the necessary conditions to make the modification appear. The minimal footprint, however, comes at the cost of a small window of attack opportunities. Experimental results show that malicious users can gain escalated privileges within a few million clock cycles. In addition, no system crashes were reported during normal operation, rendering the modifications transparent to the end user. View full abstract»

    Open Access

Aims & Scope

IEEE Transactions on Emerging Topics in Computing publishes papers on emerging aspects of computer science, computing technology, and computing applications not currently covered by other IEEE Computer Society Transactions.

Additional Information:

TETC is an open access journal. Some examples of emerging topics in computing include: IT for Green, Synthetic and organic computing structures and systems, Advanced analytics, Social/occupational computing, Location-based/client computer systems, Morphic computer design, Electronic game systems, & Health-care IT.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Fabrizio Lombardi
Department of Electrical and Computer Engineering
Northeastern University