By Topic

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 4 • Date Apr 1994

Filter Results

Displaying Results 1 - 11 of 11
  • Symbolic model checking for sequential circuit verification

    Page(s): 401 - 424
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2324 KB)  

    The temporal logic model checking algorithm of Clarke, Emerson, and Sistla (1986) is modified to represent state graphs using binary decision diagrams (BDD's) and partitioned transition relations. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5×10120 states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to express a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach

    Page(s): 425 - 438
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1172 KB)  

    A new scheduling algorithm for dataflow graphs with nested conditional branches is presented. The algorithm employs a bottom-up approach to transform a dataflow graph with conditional branches into an “equivalent” one that has no conditional branches. A schedule is then obtained for the latter, using a conventional scheduling algorithm, from which a schedule for the former is derived. Our approach is particularly effective when there is a large number of nested conditional branches in a dataflow graph View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays

    Page(s): 471 - 481
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (960 KB)  

    Proposes an optimization procedure for the bipolar base doping profile for a high-speed BiCMOS circuit. This procedure aims to achieve the minimum propagation delay time, taking the power supply, the load capacitance, and the bipolar device layout into consideration. For a small load capacitance, the peak base doping concentration and the base width should be as small as possible. However, for a high load capacitance, the optimized base doping profile can vary under the emitter area constraint. Utilizing this optimization procedure, it will be shown that the propagation delay time can be reduced by more than 30% at the same MOS current (IMOS=1 mA) through the coordinated reduction of both the vertical doping profile and the horizontal dimensions of the bipolar transistor, with the power supply voltage scaled from 5 to 3.3 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation

    Page(s): 507 - 514
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    Presents a physical model of reverse short-channel effects on threshold voltage caused by lateral diffusion of the Frenkel pairs (interstitial-vacancy) induced by ion implantation in source/drain region of n-channel MOS devices. Based on the process and device simulation, it is shown that lateral diffusion of the Frenkel pairs enhances diffusion of channel dopant, and results in nonuniform lateral distribution. This phenomenon causes the threshold voltage increase in the short-channel devices. The authors extracted parameters on point-defect diffusion from the comparison of calculated results with experimental data on threshold voltage. Calculated arsenic profile in the source/drain region using those parameters shows good agreement with the experimental data measured by secondary ion mass spectroscopy (SIMS). The close agreement between simulation and experimental results both on the arsenic profile in source/drain region and threshold voltage confirms the validity of the model and extracted parameters View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On necessary and nonconflicting assignments in algorithmic test pattern generation

    Page(s): 515 - 530
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1532 KB)  

    Necessary, nonconflicting, and arbitrary assignments can be distinguished during algorithmic test pattern generation. The identification of necessary and nonconflicting assignments is algorithmic in the sense that there is no element of choice or luck in the computation, no reliance on heuristics, and no possibility of these assignments causing a backtrack if the fault is testable. This paper presents algorithms based on the mathematical properties of images and inverse images of set functions to define reduction and tendency lists in combinational logic circuits, used to identify necessary and nonconflicting assignments, respectively. Issues relating to the efficient implementation of these algorithms are addressed from both a theoretical and practical perspective. Experimental results obtained on a variety of benchmark circuits show that algorithmic assignment identification can be used to reduce or eliminate backtracking in automatic test pattern generation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices

    Page(s): 482 - 493
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1008 KB)  

    Previous work on electrothermal simulation using network analysis techniques has been of limited use due to the lack of avalanche breakdown modeling capability and the models to efficiently describe the temperature dynamics. Particularly, simulation of electrical overstress (EOS) and electrostatic discharge (ESD), which are important threats to IC reliability, require an accurate description of temperature-dependent device electrical behaviour including breakdown phenomenon. This paper presents electrothermal device models and their implementation in a new circuit-level electrothermal simulator iETSIM. Simulation results for an I/O protection device in an advanced MOS process are presented to demonstrate iETSIM's ability to accurately model device behaviour up to the onset of second breakdown View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • PBS: proven Boolean simplification

    Page(s): 459 - 470
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1100 KB)  

    We describe PBS, a formally proven implementation of multi-level logic synthesis based on the weak division algorithm. We have proved that for all legal input circuits, PBS generates an output circuit that is functionally correct and has minimal size. PBS runs on large examples in reasonable time for a prototype system. PBS, was verified using the Nuprl proof development system. The proof of PBS, which required several months, was well worth the effort since the benefits are realized every time the program is run. When engineers use a verified synthesis tool, they get the increased confidence of applying formal methods to their designs without the cost of varying each design produced View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault simulation for multiple faults by Boolean function manipulation

    Page(s): 531 - 535
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    We propose a fault simulation technique for multiple faults based on a deductive fault simulation method. The main difficulty in the development of a technique for multiple fault simulation is handling a very large number of multiple faults. Conventional deductive simulation using Linear lists to store fault sets is not appropriate for such large sets of multiple faults. Our approach to this problem is to represent sets of multiple faults by Boolean functions. We assign a distinct code word to each multiple fault and represent the fault by a minterm corresponding to its code word. Then, set operations in deductive simulation are replaced by logic operations. As an internal representation of fault sets, we use shared binary decision diagrams. The method of coding multiple faults is a key to efficient simulation. We propose a coding method called FNT coding. We also propose a fault dropping method, called prime fault dropping, which is used efficiently with our multiple fault simulation technique. Experimental results show that our technique effectively handles multiple faults at significantly lower computation cost View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An SOS MOSFET model based on calculation of the surface potential

    Page(s): 494 - 506
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1184 KB)  

    A circuit simulation model is presented suitable for the design of analogue and digital SOS MOSFET integrated circuits. Both the drift and diffusion components of channel current are modeled, which are computed from the surface potentials at the drain and source ends of the channel. The surface potential function varies continuously from subthreshold to strong inversion allowing a smooth transition of device conductances and capacitances at the threshold voltage. Charge is conserved in the model formulation yielding reliable simulation results in transient analysis. The model has been implemented in the SPICE program, together with important extrinsic elements such as impact ionization current, pn-junction current and capacitances, and substrate resistance. The pn-junction current expression includes a physical formulation for the drain leakage current. The influence of temperature on device characteristics is included, making the model valid from -55 to 125°C. Simulation results are compared with measured dc device characteristics showing considerable improvement over bulk MOS models in predicting the drain conductance. In subthreshold, the model predicts the observed increase in inverse subthreshold slope with drain bias for n-channel devices. Transient simulations show that capacitive coupling from drain, gate and source nodes can strongly influence the floating substrate potential. The model has been successfully applied to the design of analogue SOS circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Lower-bound performance estimation for the high-level synthesis scheduling problem

    Page(s): 451 - 458
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (668 KB)  

    A given behavioral specification can be implemented on a large number of register-transfer level designs. Instead of producing several designs and selecting the best one, synthesis systems may use estimation to reduce the design space. In this paper, we present a new technique for computing a lower-bound completion time for non-pipelined resource-constrained scheduling problem. Given a data flow graph, a set of resources, resource delays and a clock cycle, we derive a lower-bound on the completion time of a schedule. Our technique can handle chaining, multi-cycle operations and pipelined modules. The technique is very fast and experimental results show that it is also very tight View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A transformation-based method for loop folding

    Page(s): 439 - 450
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1052 KB)  

    We propose a transformation-based scheduling algorithm for the problem given a loop construct, a target initiation interval and a set of resource constraints, schedule the loop in a pipelined fashion such that the iteration time of executing an iteration of the loop is minimized. The iteration time is an important quality measure of a data path design because it affects both storage and control costs. Our algorithm first performs an As Soon As Possible Pipelined (ASAPp) scheduling regardless the resource constraint. It then resolves resource constraint violations by rescheduling some operations. The software system implementing the proposed algorithm, called Theda.Fold, can deal with behavioral loop descriptions that contain chained, multicycle and/or structural pipelined operations as well as those having data dependencies across iteration boundaries. Experiment on a number of benchmarks is reported View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu