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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 6 • Date June 2014

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Displaying Results 1 - 25 of 31
  • Table of contents

    Publication Year: 2014 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2014 , Page(s): C2
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    Freely Available from IEEE
  • A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process

    Publication Year: 2014 , Page(s): 1609 - 1617
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1690 KB) |  | HTML iconHTML  

    This paper presents a 60-dB gain bulk-driven Miller OTA operating at 0.25-V power supply in the 130-nm digital CMOS process. The amplifier operates in the weak-inversion region with input bulk-driven differential pair sporting positive feedback source degeneration for transconductance enhancement. In addition, the distributed layout configuration is used for all the transistors to mitigate the effect of halo implants for higher output impedance. Combining these two approaches, we experimentally demonstrate a high gain of over 60-dB with just 18-nW power consumption from 0.25-V power supply. The use of enhanced bulk-driven differential pair and distributed layout can help overcome some of the constraints imposed by nanometer CMOS process for high performance analog circuits in weak inversion region. View full abstract»

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  • CMOS Startup Charge Pump With Body Bias and Backward Control for Energy Harvesting Step-Up Converters

    Publication Year: 2014 , Page(s): 1618 - 1628
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1565 KB) |  | HTML iconHTML  

    A new low voltage charge pump is developed to help start up a step-up converter in energy harvesting applications. The proposed charge pump is the first to utilize both backward control scheme and two branches of charge transfer switches (CTSs) to direct charge flow. The backward control scheme uses the internal boosted voltage to dynamically control the CTSs' gate, and the two branches utilize both NMOS and PMOS to implement their switching structure. The combination of backward control scheme and two-branch operation allows the CTSs to be completely turned on and off. Thus, the reverse charge sharing phenomenon and switching loss are significantly reduced, which effectively improves pumping efficiency. The last stage is specially designed to improve the charge pump's charge and capacitance drivability. Using subthreshold operation and body-bias technique, the charge pump and its clock generator can operate under a low voltage supply. The proposed charge pump circuit is designed in a standard 0.18 μm CMOS process. It consists of 6 stages, each with a 24 pF pumping capacitor (total 288 pF pumping capacitance area). Under a 320 mV supply, the measured output voltage of the proposed charge pump can rise from 0 to 2.04 V within 0.1 milliseconds. View full abstract»

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  • Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments

    Publication Year: 2014 , Page(s): 1629 - 1637
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    We present a technique for determining the coefficients of the loop filter in a continuous-time delta sigma modulator (CTDSM) from the corresponding discrete time prototype. The method, which is based on computing the moments of the feedback DAC pulse shape, enables the determination of loop filter coefficients to an arbitrary DAC pulse shape without resorting to z-domain analysis. This not only simplifies the algebra, but also gives new insights into modulator operation. The technique helps derive topologies to compensate CTDSMs with FIR feedback DACs, as well as give closed form expressions for the coefficients of the compensated modulator. Finally, we give simple formulae for coefficients to compensate for excess loop delay in CTDSMs with arbitrary DAC pulses. View full abstract»

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  • Applications of Body Biasing in Multistage CMOS Low-Noise Amplifiers

    Publication Year: 2014 , Page(s): 1638 - 1647
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1498 KB) |  | HTML iconHTML  

    Low-noise amplifiers (LNAs) are one of the important building blocks of wireless receivers. LNA design parameters such as gain, noise figure, linearity, input matching, and stability are important metrics and typically affect the overall performance of the receiver. The strong trade-offs among these design parameters often necessitate several design iterations. While many of these trade-offs are due to the nature of the circuit and are inevitable, it is desirable to decouple the effects of each parameter on the others. In this work, body biasing is introduced as a technique to enhance the linearity, to improve the noise figure and to provide gain variation. These techniques are presented in the context of a three-stage LNA. By applying body biasing in each stage, noise figure, gain variation and linearity of the overall amplifier are adjusted almost independently, i.e., with minimal interrelation among these design parameters. As a proof-of-concept, a prototype 4.4-GHz LNA is designed and fabricated in a 0.13- μm CMOS technology. The LNA achieves a minimum noise figure of 3.8 dB, maximum gain of 20.2 dB, and a maximum IIP3 of -14 dBm while consuming 3.6 mW from a 1.2 V supply. View full abstract»

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  • A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition

    Publication Year: 2014 , Page(s): 1648 - 1655
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    A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm2. The PLL locking time is less than 3 μs. This chip drains 24 mW from a 1.2 V power supply. View full abstract»

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  • A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer

    Publication Year: 2014 , Page(s): 1656 - 1665
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2416 KB) |  | HTML iconHTML  

    Wide-range level shifters play critical roles in ultra- low-voltage circuits and systems. Although state-of-the-art level shifters can convert a subthreshold voltage to the standard supply voltage, they may have limited operating ranges, which restrict the flexibility of dynamic voltage scaling. Therefore, this paper presents a novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion. The proposed level shifter is a hybrid structure comprising a modified Wilson current mirror and generic CMOS logic gates. The simulation and measurement results were verified using a 65-nm technology. The minimal operating voltage of the proposed level shifter was less than 200 mV based on the measurement results. In addition to the operating range, the delay, power consumption, and duty cycle of the proposed level shifter were designed for practical applications. View full abstract»

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  • Current Mode Image Sensor With Improved Linearity and Fixed-Pattern Noise

    Publication Year: 2014 , Page(s): 1666 - 1674
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    Current mode active pixel sensors convert light intensity into an analog output current. A current mode image sensor enables simple implementation of focal plane algebraic functions but suffers from poor linearity and large fixed-patten noise. This paper analyzes the causes of the non-linearity of a current-mode image sensor including a theoretical derivation and numerical simulation. Previously reported linearity improvement methods are reviewed, while an architecture of a current mode image sensor with a voltage feedback loop between pixel output and the current conveyor for linearity enhancement is proposed. An image sensor array of 100 × 200 current mode pixels is fabricated in a 0.5 μm 2P3M standard CMOS processing technology. Experimental results illustrate a 45% improvement of the linearity of the proposed imager. Fixed pattern noise is reduced by 57.6% for the maximum readout current, which can be further reduced by another 51.5% after gain calibration. A signal to noise ratio of 49.6 dB is achieved. View full abstract»

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  • Extended Noise Shaping in Sigma-Delta Modulator Using Cross-Coupled Paths

    Publication Year: 2014 , Page(s): 1675 - 1686
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2970 KB) |  | HTML iconHTML  

    In this paper, combined with time-interleaving, noise coupling is used to achieve considerable improvement in the performance of sigma-delta modulator. Two types of noise-coupling, unextended and extended coupling, are presented for N-path architecture based on first-order sigma-delta modulator which can enhance the effective order of noise shaping without significant overhead. In the general condition, the optimum coupling matrices are obtained analytically to achieve the desired noise shaping. It is also shown that the proposed N-path first-order sigma-delta modulator provides (2N-1)th-order noise shaping. However, the unextended coupling provides Nth-order. To verify the proposed method, the macro-level simulations show that third-order and fifth-order noise shaping were achieved in two-path and three-path first-order sigma-delta modulators with extended noise coupling, respectively. Likewise, the ADS software's simulation result of the switched-capacitor circuit implementation confirms the effectiveness of the proposed method. View full abstract»

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  • Design of Reverse Converters for General RNS Moduli Sets { 2^{k}, 2^{n}-1, 2^{n}+1, 2^{n+1}-1 } and { 2^{k}, 2^{n}-1, 2^{n}+1, 2^{n-1}-1 } ( n even)

    Publication Year: 2014 , Page(s): 1687 - 1700
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    This paper presents the design methods of residue-to-binary (reverse) converters for two 4-moduli sets {2k, 2n-1, 2n+1, 2n+1-1} and {2k, 2n-1, 2n+1, 2n-1-1} for the pairs of positive integers n (n even) and arbitrary k > 0, which provide flexible dynamic ranges for the residue number system (RNS). These two moduli sets are generalizations of the 4-moduli sets {2n, 2n-1, 2n+1, 2n+1-1} and {2n, 2n-1, 2n+1, 2n-1-1} ( n even) with only a single parameter n. They facilitate selecting a moduli set which not only suits exactly the required dynamic range but also allows to balance delay disparity and hardware complexity between an even modulus and the odd moduli datapath channels. The new reverse converter for the moduli set {2k, 2n-1, 2n+1, 2n+1-1} not only enjoys slightly better performance than its known counterpart but also applies to arbitrary k. The reverse converter for the new moduli set {2k, 2n-1, 2n+1, 2n-1-1} is the first ever proposed. Synthesis results obtained for the 65 nm technology show that at least one of two versions of our converters is superior w.r.t. delay, power consumption, and area than its counterpart for the 4-moduli set {2k, 2n-1, 2n+1, 2n+1-1}, for all dynamic ranges from 14 to 64 bits. View full abstract»

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  • Fault Injection Modeling Attacks on 65 nm Arbiter and RO Sum PUFs via Environmental Changes

    Publication Year: 2014 , Page(s): 1701 - 1713
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1509 KB) |  | HTML iconHTML  

    Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. So-called strong PUFs provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. To prevent cloning, modeling of the challenge-response pair (CRP) behavior should be infeasible. Machine learning (ML) algorithms are a well-known threat. Recently, repeatability imperfections of PUF responses have been identified as another threat. CMOS device noise renders a significant fraction of the CRPs unstable, hereby providing a side channel for modeling attacks. In previous work, 65 nm arbiter PUFs have been modeled as such with accuracies exceeding 97%. However, more PUF evaluations were required than for state-of-the-art ML approaches. In this work, we accelerate repeatability attacks by increasing the fraction of unstable CRPs. Response evaluation faults are triggered via environmental changes hereby. The attack speed, which is proportional to the fraction of unstable CRPs, increases with a factor 2.4 for both arbiter and ring oscillator (RO) sum PUFs. Data originates from a 65 nm silicon chip and hence not from simulations. View full abstract»

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  • An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design

    Publication Year: 2014 , Page(s): 1714 - 1726
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2794 KB) |  | HTML iconHTML  

    Strain engineering for performance enhancement is an integral part of a state-of-the-art CMOS process flow. However, use of stressors makes the performance of CMOS devices layout dependent. Performance variability arising due to the use of stressor materials is often referred to as Layout Dependent Effect (LDE) variability. The existing delay models do not take LDE into consideration and, therefore, results into unaccounted change in performance and degraded design robustness. In this paper we propose an analytical delay model for Inverter, 2-input NAND and NOR gates while considering LDE variability due to the use of strain engineered devices. We compare our derived model with TCAD calibrated HSPICE simulation results and observe that our model estimates delay well for varying transistor sizes, load capacitances and input signal transition times. View full abstract»

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  • Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

    Publication Year: 2014 , Page(s): 1727 - 1740
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3132 KB) |  | HTML iconHTML  

    Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT transforms have been proposed that offer superior compression performance at very low circuit complexity. Such approximations can be realized in digital VLSI hardware using additions and subtractions only, leading to significant reductions in chip area and power consumption compared to conventional DCTs and integer transforms. In this paper, we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio. The proposed DCT approximation is a candidate for reconfigurable video standards such as HEVC. The proposed transform and several other DCT approximations are mapped to systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology. View full abstract»

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  • Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures

    Publication Year: 2014 , Page(s): 1741 - 1754
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    Power efficiency of embedded systems is a tremendous challenge within the context of platforms with limited power-budget and high computational performance. These conflicting design objectives can be met if both the clock frequency and the supply voltage are dynamically controlled with respect to the ongoing application requirement. As a result, a new trend has appeared in the design of MultiProcessor Systems-on-Chips. It aims at managing the clock frequency and supply voltage of each power domain independently. However, this trend raises some new design challenges. Among them, monitoring at fine-grain and on the fly the operating conditions of each power domain using low-cost on-chip sensors is of great interest. This paper deals with this challenge. It proposes a novel approach based on the integration, either in hardware or in software, of a goodness-of-fit statistical test to interpret data acquired from low-cost and fully digital sensors embedded in each power domain. After a discussion about the accuracy, efficiency and costs of the proposed approach, the voltage reductions that can be achieved for various performance targets are given. View full abstract»

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  • Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

    Publication Year: 2014 , Page(s): 1755 - 1765
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2411 KB) |  | HTML iconHTML  

    Advanced computing systems suffer from high static power due to the rapidly rising leakage currents in deep sub-micron MOS technologies. Fast access non-volatile memories (NVM) are under intense investigation to be integrated in Flip-Flops or computing memories to allow system power-off in standby state and save power. Spin Transfer Torque MRAM (STT-MRAM) is considered the most promising NVM to address this issue thanks to its high speed, low power, and infinite endurance. However, one of the disadvantages of STT-MRAM for the computing purpose is its relatively high write energy to build up Magnetic Flip-Flop (MFF). In this paper, we propose a power-efficient MFF design architecture to address this challenge based on the combination of checkpointing operation, power gating and self-enable mechanisms. Multi non-volatile storages can be integrated locally in a conventional FF without significant area overhead benefiting from the 3-D implementation of STT-MRAM. We performed electrical simulations (i.e. transient and statistical) to validate its functional behaviors and evaluate its performance by using an accurate spice model of STT-MRAM and an industrial 40 nm CMOS design kit. The simulation results confirm its lower power consumption compared to conventional CMOS FF and the other structures. View full abstract»

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  • Add-Equalize Structures for Linear-Phase Nyquist FIR Filter Interpolators and Decimators

    Publication Year: 2014 , Page(s): 1766 - 1777
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2354 KB) |  | HTML iconHTML  

    This paper introduces add-equalize structures for the implementation of linear-phase Nyquist (M th-band) finite-length impulse response (FIR) filter interpolators and decimators. The paper also introduces a systematic design technique for these structures based on iteratively reweighted ℓ1-norm minimization. In the proposed structures, the polyphase components share common parts which leads to a considerably lower implementation complexity as compared to conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist structures. A main advantage of the proposed structures is that they work equally well for all integer conversion factors, thus including prime numbers which cannot be handled by the regular multi-stage Nyquist converters. Moreover, the paper shows how to utilize the frequency-response masking approach to further reduce the complexity for sharp-transition specifications. It also shows how the proposed structures can be used to reduce the complexity for reconfigurable sampling rate converters. Several design examples are included to demonstrate the effectiveness of the proposed structures. View full abstract»

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  • Finite-Time Synchronization of a Class of Second-Order Nonlinear Multi-Agent Systems Using Output Feedback Control

    Publication Year: 2014 , Page(s): 1778 - 1788
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3544 KB) |  | HTML iconHTML  

    This paper considers the problem of finite-time synchronization for a class of second-order nonlinear multi-agent systems with a leader-follower architecture. By using the finite-time control technique and homogenous systems theory, a finite-time state feedback controller is first proposed. Then to address the lack of velocity measurement, a finite-time convergent observer is constructed to estimate the unknown velocity information in a finite time. Finally, an observer-based finite-time output feedback controller is developed. Rigorous proof shows that the systems output can reach synchronization in a finite time and the final consensus states are the leader's states. In addition, for some special second-order multi-agent systems, a bounded finite-time output feedback controller can also be designed. View full abstract»

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  • Input-to-State Stability for Nonlinear Systems With Large Delay Periods Based on Switching Techniques

    Publication Year: 2014 , Page(s): 1789 - 1800
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    The paper is concerned with the problem of input-to-state stability (ISS) for nonlinear delay systems with large delay periods (LDP). The concepts of the length rate of LDP and the frequency of LDP are introduced. First the considered system is converted into a switched delay system which may include an unstable subsystem. Then based on a piecewise Lyapunov functional, the ISS properties of the systems are developed under the constraints of the length rate and the frequency of LDP. ISS for a special kind of nonlinear delay systems is also considered and the conditions of nonlinear matrix inequalities (NLMIs) are proposed to guarantee the ISS properties of such a system. A numerical example and an example of a series DC motor are given to show the effectiveness of the proposed methods. View full abstract»

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  • Synchronization of Identical Linear Systems and Diffusive Time-Delayed Couplings

    Publication Year: 2014 , Page(s): 1801 - 1814
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    We study the problem of controlled network synchronization for a class of identical linear systems. The systems are interconnected through static and dynamic diffusive couplings with time-delays. In particular, we derive conditions on the systems, on the couplings, on the time-delay, and on the network topology that guarantee global synchronization of the systems. Diffusive time-delayed dynamic couplings are constructed by combining linear observers and output feedback controllers. Using passivity properties, sufficient conditions for boundedness of the interconnected systems are derived. Moreover, predictor-based dynamic couplings are proposed in order to enhance robustness against time-delays in the network. The results are illustrated by numerical simulations. View full abstract»

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  • Model Order Reduction of Time-Delay Systems Using a Laguerre Expansion Technique

    Publication Year: 2014 , Page(s): 1815 - 1823
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    The demands for miniature sized circuits with higher operating speeds have increased the complexity of the circuit, while at high frequencies it is known that effects such as crosstalk, attenuation and delay can have adverse effects on signal integrity. To capture these high speed effects a very large number of system equations is normally required and hence model order reduction techniques are required to make the simulation of the circuits computationally feasible. This paper proposes a higher order Krylov subspace algorithm for model order reduction of time-delay systems based on a Laguerre expansion technique. The proposed technique consists of three sections i.e., first the delays are approximated using the recursive relation of Laguerre polynomials, then in the second part, the reduced order is estimated for the time-delay system using a delay truncation in the Laguerre domain and in the third part, a higher order Krylov technique using Laguerre expansion is computed for obtaining the reduced order time-delay system. The proposed technique is validated by means of real world numerical examples. View full abstract»

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  • Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems

    Publication Year: 2014 , Page(s): 1824 - 1835
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    Turbo decoders for modern wireless communication systems have to support high throughput over a wide range of code rates. In order to support the peak throughputs specified by modern standards, parallel turbo-decoding has become a necessity, rendering the corresponding VLSI implementation a highly challenging task. In this paper, we explore the implementation trade-offs of parallel turbo decoders based on sliding-window soft-input soft-output (SISO) maximum a-posteriori (MAP) component decoders. We first introduce a new approach that allows for a systematic throughput comparison between different SISO-decoder architectures, taking their individual trade-offs in terms of window length, error-rate performance and throughput into account. A corresponding analysis of existing architectures clearly shows that the latency of the sliding-window SISO decoders causes diminishing throughput gains with increasing degree of parallelism. In order to alleviate this parallel turbo-decoder predicament, we propose a new SISO-decoder architecture that leads to significant throughput gains and better hardware efficiency compared to existing architectures for the full range of code rates. View full abstract»

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  • A 90 nm-CMOS IR-UWB BPSK Transmitter With Spectrum Tunability to Improve Peaceful UWB-Narrowband Coexistence

    Publication Year: 2014 , Page(s): 1836 - 1848
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    A new ultra wideband (UWB) pulse generator covering a -10 dB bandwidth of 2.4-4.6 GHz with a tunable center frequency of 5-5.6 GHz to mitigate coexistence issues of impulse radio UWB (IR-UWB) systems and IEEE802.11.a WLAN or other narrowband (NB) systems in 90 nm-CMOS technology is proposed. The UWB pulse is generated based on frequency up-conversion of the first derivative of the Gaussian pulse, which creates an adjustable null in the frequency spectrum. Simulation results show that employing the proposed pulse generator mitigates the mutual interference between UWB and WLAN systems, significantly. The proposed transmitter consists of a low frequency signal generator, an LC oscillator and a mixer, whose output directly drives the antenna using a matching on-chip transformer. Two control signals change the bandwidth and center frequency of the transmitted spectrum depending on the NB frequency and considering process, supply voltage and temperature (PVT) variations. A fast start-up circuit is used in the LC oscillator using current pulse injection and together with the mixer is duty cycled to reduce the power consumption. Post-layout simulation results show a null depth of 23 dB for a null bandwidth of 100 MHz. The energy/pulse and energy/pulse normalized to the output voltage amplitude are 14.4 pJ/pulse and 35.7 pJ/(pulse-V) from a 1-V supply for a pulse rate of 860 Mpulse/s with an active circuit area of only 0.18 mm2. View full abstract»

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  • Blind Self-Calibration Technique for I/Q Imbalances and DC-Offsets

    Publication Year: 2014 , Page(s): 1849 - 1859
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    The gain/phase imbalances and DC-offsets in the in-phase and quadrature branches in direct conversion transmitters (DCTs) are main sources of errors, especially at microwave frequencies and above. These impairments distort the spectrum of the transmitted signal and degrade the communications performance. In this paper, a blind technique based on higher order statistics is proposed to estimate the calibration parameters in order to compensate for these impairments. By minimizing a cost function composed of second and fourth moments of the modulator output signal, the DC-offsets, gain imbalance, and phase imbalance can be successively calibrated. The convergence of the proposed technique is also analyzed. This technique is blind in the sense that it does not require any prior knowledge about the DCT input signal, and is applicable to many communications systems including QAM, OFDM, and SC-FDMA. Computer simulations and experiments at 20 GHz demonstrate that the proposed technique can significantly improve the DCT performance in terms of local oscillator leakage and image suppressions. View full abstract»

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  • A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s

    Publication Year: 2014 , Page(s): 1860 - 1871
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2048 KB) |  | HTML iconHTML  

    In this paper, a VLSI implementation of a complete MIMO channel equalization ASIC based on lattice reduction-aided linear detection is presented. The architecture performs preprocessing steps at channel rate and low-complexity linear data detection at symbol rate. Preprocessing is based on Seysen's algorithm for lattice reduction. We present algorithmic improvements of the lattice reduction preprocessing in terms of area and throughput of the VLSI implementation with minor impact on the error-rate. Due to the low-complexity implementation of the lattice reduction-aided data detection stage, our architecture is able to achieve very low power in typical packet-based MIMO wireless data transmission scenarios. The final 90 nm CMOS ASIC achieves an energy efficiency for the detection of 24 pJ/bit at a throughput of 720 Mbps with near-optimal error-rate performance. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras