IEEE Embedded Systems Letters

Issue 2 • June 2014

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Displaying Results 1 - 10 of 10
  • Table of contents

    Publication Year: 2014, Page(s): C1
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  • IEEE Embedded Systems Letters publication information

    Publication Year: 2014, Page(s): C2
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  • PEG-C: Performance Enhancement Guaranteed Cache for Hard Real-Time Systems

    Publication Year: 2014, Page(s):17 - 20
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB) | HTML iconHTML

    This letter designs the performance enhancement guaranteed cache (PEG-C) for hard real-time systems. The PEG-C uses two counters to monitor the number of hits and misses at runtime to improve the average-case performance, while guaranteeing the worst-case execution time (WCET). Our experiments indicate that with a few preloaded instructions, a PEG instruction cache can achieve the same average-cas... View full abstract»

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  • High Communication Throughput and Low Scan Cycle Time with Multi/Many-Core Programmable Logic Controllers

    Publication Year: 2014, Page(s):21 - 24
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB) | HTML iconHTML

    Programmable logic controllers (PLCs) are hard real-time embedded systems designed to interact with (through sensors and actuators) and control physical processes in pharmaceutical, manufacturing, energy, and automotive industries. PLCs are the fundamental building blocks in modern industrial automation systems; they are designed to operate in extreme, harsh environments for decades without interr... View full abstract»

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  • Runtime Adaptation of Applications Using Design Of Experiments: A Smartphone-Based Case Study

    Publication Year: 2014, Page(s):25 - 28
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB) | HTML iconHTML

    We consider the problem of adapting embedded software to heterogeneous devices where it is impractical to obtain a system-level power model for each target platform and operating environment. Our solution leverages the emerging capability of measuring power consumption at run-time using a built-in battery monitoring unit (BMU). We use a statistically rigorous design of experiments (DoE) methodolog... View full abstract»

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  • A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices

    Publication Year: 2014, Page(s):29 - 32
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB) | HTML iconHTML

    Low density parity check (LDPC) decoding process is known as compute intensive. This kind of digital communication applications was recently implemented onto graphic processing unit (GPU) devices for LDPC code performance estimation and/or for real-time measurements. Overall previous studies about LDPC decoding on GPU were based on the implementation of the flooding-based decoding algorithm that p... View full abstract»

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  • Selective Segment Initialization: Exploiting NVRAM to Reduce Device Startup Latency

    Publication Year: 2014, Page(s):33 - 36
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (542 KB) | HTML iconHTML

    We propose selective segment initialization (SSI) to exploit NVRAM to reduce the device startup latency. SSI locates a kernel binary image in byte-addressable NVRAM and boots the system using this image, eliminating the need to load it from storage. SSI also eliminates the process of decompressing and relocating the OS kernel image in embedded Linux system. The key technical ingredients of SSI are... View full abstract»

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  • SIMON Says: Break Area Records of Block Ciphers on FPGAs

    Publication Year: 2014, Page(s):37 - 40
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (545 KB) | HTML iconHTML

    While advanced encryption standard (AES) is extensively in use in a number of applications, its area cost limits its deployment in resource constrained platforms. In this letter, we have implemented SIMON, a recent promising low-cost alternative of AES on reconfigurable platforms. The Feistel network, the construction of the round function and the key generation of SIMON, enables bit-serial hardwa... View full abstract»

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  • IEEE Embedded Systems Letters information for authors

    Publication Year: 2014, Page(s): C3
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  • [Blank page - back cover]

    Publication Year: 2014, Page(s): C4
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Aims & Scope

The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

Meet Our Editors

EDITOR-IN-CHIEF
Sri Parameswaran
School of Computer Science and Engineering
University of New South Wales

DEPUTY EDITOR-IN-CHIEF
Tulika Mitra
School of Computing
National University of Singapore