# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 21 of 21

Publication Year: 2014, Page(s): C1
| PDF (42 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2014, Page(s): C2
| PDF (136 KB)
• ### A Wideband Dual-Mode $LC$-VCO With a Switchable Gate-Biased Active Core

Publication Year: 2014, Page(s):289 - 293
Cited by:  Papers (7)
| | PDF (859 KB) | HTML

A wideband inductance-capacitance voltage-controlled oscillator (VCO) with a gm-switching technique was designed and fabricated in the 65-nm CMOS process. With a switchable secondary gate-biased active core and a primary core, the VCO operates in two different modes. In the LF mode, in which switches turn on the secondary core, the increased start-up gain facilitates LF oscillation. In ... View full abstract»

• ### An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs

Publication Year: 2014, Page(s):294 - 298
Cited by:  Papers (10)
| | PDF (532 KB) | HTML

This brief presents a highly energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters that achieves a 95% reduction in switching energy over the conventional SAR. The switching energy has been calculated by taking into account both the power drawn from reference and the power consumed by the switches themselves. The frequency dependence of the swit... View full abstract»

• ### A Practical Implementation of a Floating Memristor-Less Meminductor Emulator

Publication Year: 2014, Page(s):299 - 303
Cited by:  Papers (7)
| | PDF (480 KB) | HTML

A meminductor, a nonlinear two-terminal device with memory and energy storage ability, is generalized on the basis of the conception of a memristor. To date, the meminductor is commonly unavailable; therefore, it is of great significance to build a meminductor emulator in hardware. In this brief, a practical floating flux-controlled meminductor emulator is designed without using a memristor. Moreo... View full abstract»

• ### A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process

Publication Year: 2014, Page(s):304 - 308
Cited by:  Papers (2)
| | PDF (732 KB) | HTML

This brief describes the design of a four-channel 32-Gb/s serial link transmitter with a current-recycling output driver and an on-chip ac-coupled receiver. The proposed output driver significantly reduces power dissipation in the final stage of the transmitter by reusing the natural current flow through the four-channel outputs. It also eliminates the voltage regulation circuit and the current so... View full abstract»

• ### A Floating Analog Memristor Emulator Circuit

Publication Year: 2014, Page(s):309 - 313
Cited by:  Papers (25)  |  Patents (1)
| | PDF (446 KB) | HTML

This brief introduces a new floating memristor emulator circuit based on second-generation current conveyors and passive elements. A mathematical model to characterize the memristor behavior was derived, showing a good accuracy among HSPICE simulations and experimental results. An analysis of the frequency behavior of the memristor is also described, showing that the frequency-dependent pinched hy... View full abstract»

• ### A Subgigahertz UWB Transmitter With Wireless Clock Harvesting for RF-Powered Applications

Publication Year: 2014, Page(s):314 - 318
Cited by:  Papers (2)
| | PDF (1128 KB) | HTML

A subgigahertz ultrawideband (UWB) transmitter (TX) with wireless clock harvesting is presented for RF-powered applications such as RF identifications and implantable devices in the 180-nm CMOS process. The proposed low-power TX consists of a harmonic injection-locked ring oscillator (ILRO), a synchronized pulse generator, and a driver stage. Through wireless injection locking, a 450-MHz carrier i... View full abstract»

• ### A 0.4-V, 90 $\sim$ 350-MHz PLL With an Active Loop-Filter Charge Pump

Publication Year: 2014, Page(s):319 - 323
Cited by:  Papers (6)
| | PDF (1383 KB) | HTML

A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibrati... View full abstract»

• ### A 2.1-Channel Class-D Amplifier Exploited Coupling Virtual-Audio-Image to Enhance Stereo

Publication Year: 2014, Page(s):324 - 328
| | PDF (834 KB) | HTML

This brief presents a novel 2.1-channel stereoenhanced class-D audio amplifier to improve the quality of stereophonic sound in portable devices. By a way of cross coupling, the input audio signal from one channel can be amplified at the same time, with different gains in the two channels. The ratio of gains in the two channels can be adjusted by changing the resistance and then making the position... View full abstract»

• ### Dynamic Performance Characterization of Embedded Single-Ended Mixed-Signal Circuits

Publication Year: 2014, Page(s):329 - 333
Cited by:  Papers (1)
| | PDF (297 KB) | HTML

The inherent fault-masking characteristic of the traditional loopback test produces overly pessimistic estimates of device-under-test (DUT) performance, which negatively impacts product yield, although the loopback test provides a promising low-cost test solution. The proposed method overcomes the fault-masking shortcomings of the loopback test for single-ended mixed-signal circuits by accurately ... View full abstract»

• ### A 1.2-MHz 5.8- $\mu\hbox{W}$ Temperature-Compensated Relaxation Oscillator in 130-nm CMOS

Publication Year: 2014, Page(s):334 - 338
Cited by:  Papers (5)
| | PDF (716 KB) | HTML

This brief presents a low-power temperature-compensated relaxation oscillator in 130-nm CMOS for cubic millimeter wireless sensor node applications. An RC network is proposed for the oscillator, which introduces a zero in the transfer function, creating an additional degree of freedom in the step response used for frequency-temperature compensation. This approach uses conventional CMOS resistor an... View full abstract»

• ### A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS

Publication Year: 2014, Page(s):339 - 343
Cited by:  Papers (4)
| | PDF (867 KB) | HTML

This brief presents a single-channel two-step successive approximation register (SAR) analog-to-digital converter (ADC) using a source follower as an interstage residue amplifier. An asynchronous SAR ADC with two-step timing can effectively allocate the bit-resolving procedure into the whole clock period and eliminate a dedicated duty-cycle clock generator. The arbitrary weight capacitor array tec... View full abstract»

• ### In Situ Power Gating Efficiency Learner for Fine-Grained Self-Adaptive Power Gating

Publication Year: 2014, Page(s):344 - 348
Cited by:  Papers (1)
| | PDF (1079 KB) | HTML

A low-power in situ learner circuit is presented to characterize the tradeoff between leakage saving and transition energy overhead in power gating (PG). A self-adaptive PG scheme is demonstrated that utilizes the learner circuit to adaptively invoke PG only when leakage saving is more than the transition energy overhead. A 130-nm test chip demonstrates functionality of the learner circuit and its... View full abstract»

• ### Radix- $2^{r}$ Arithmetic for Multiplication by a Constant

Publication Year: 2014, Page(s):349 - 353
Cited by:  Papers (9)
| | PDF (928 KB) | HTML

In this brief, radix-2r arithmetic is explored to minimize the number of additions in the multiplication by a constant. We provide the formal proof that, for an N-bit constant, the maximum number of additions using radix- 2ris lower than Dimitrov's estimated upper bound 2. N/log(N) using the double-base number system (DBNS). In comparison with the canonical signed digit (CSD)... View full abstract»

• ### Realizing Unequal Error Correction for nand Flash Memory at Minimal Read Latency Overhead

Publication Year: 2014, Page(s):354 - 358
Cited by:  Papers (2)
| | PDF (738 KB) | HTML

In nand Flash memory, all pages have the same storage capacity and hence accommodate the same amount of redundancy in support of error correction. In current practice, user data in all the pages are protected by the same error correction code. However, different types of pages in multibit per cell memory have largely different bit error rates, for which appropriate unequal error correction can ach... View full abstract»

• ### Distributed ${\cal H}_{\infty}$ Consensus of Higher Order Multiagent Systems With Switching Topologies

Publication Year: 2014, Page(s):359 - 363
Cited by:  Papers (40)
| | PDF (137 KB) | HTML

This brief addresses the distributed H∞ consensus problem of multiagent systems with higher order linear dynamics and switching directed topologies. Without assuming that the directed communication topology is fixed or balanced, a class of distributed protocols is constructed and employed to achieve state consensus while guaranteeing a prescribed disturbance rejection objective, ... View full abstract»

• ### Convergence Analysis of an Adaptive Algorithm With Output Power Constraints

Publication Year: 2014, Page(s):364 - 367
| | PDF (300 KB) | HTML

This brief presents a convergence analysis and simulation for a new algorithm intended for use in systems with an output power constraint. For example, in an active noise control system that generates an antinoise output to destructively cancel the noise source, we impose the additional requirement of limiting the maximum output power level to prevent system overdrive. The result is a computationa... View full abstract»

• ### On the Designs of Variable Fractional Hilbert Transformers

Publication Year: 2014, Page(s):368 - 372
Cited by:  Papers (8)
| | PDF (517 KB) | HTML

In this brief, the designs of variable fractional Hilbert transformers (VFHTs) are presented. First, the definition and properties of FHT are briefly reviewed. Then, the fact that the frequency response of FHT with order v can be obtained from the linear combination of those of the two FHTs with different orders p and q will be shown. Based on this fact, a new VFHT structure is derived, in which t... View full abstract»

• ### IEEE Circuits and Systems Society Information

Publication Year: 2014, Page(s): C3
| PDF (119 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2014, Page(s): C4
| PDF (108 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org