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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 5 • Date May 2014

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Displaying Results 1 - 25 of 34
  • Table of contents

    Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): C2
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    Freely Available from IEEE
  • Guest Editorial Special Section on the 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013)

    Page(s): 1301 - 1303
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  • A FVF LDO Regulator With Dual-Summed Miller Frequency Compensation for Wide Load Capacitance Range Applications

    Page(s): 1304 - 1312
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    This paper presents a proposed Flipped Voltage Follower (FVF) based output capacitorless low-dropout (OCL-LDO) regulator using Dual-Summed Miller Frequency Compensation (DSMFC) technique. Validated by UMC 65-nm CMOS process, the simulation results have shown that the proposed LDO regulator can be stabilized by a total compensation capacitance (CC) of 8 pF for a load capacitance (CL) ranging from 10 pF to 10 nF. It consumes 23.7 μA quiescent current with a 1.2 V supply voltage. With a dropout voltage of 200 mV, the LDO regulator can support a maximum 50 mA load current. It can settle in less than 1.7 μs with a 1% accuracy for the whole CL range. The proposed LDO regulator is comparable to other reported works in terms of figure-of-merit (FOM). Most significantly, it can drive the widest range of CL and achieve the highest CL(max)/CC ratio with respect to the counterparts. View full abstract»

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  • Characterization Techniques for High Speed Oversampled Data Converters

    Page(s): 1313 - 1320
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    Bench characterization of wide band oversampled converters is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feedthrough effects. Experimental results from a test chip in 90 nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing single-bit CTDSM from 3.6 GHz to 4.4 GHz. View full abstract»

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  • A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter

    Page(s): 1321 - 1330
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    A novel highly-efficient multi-band multi-mode all-digital quadrature transmitter is presented. In the transmitter, a switching-mode power amplifier (PA), also referred to as digital power amplifier (DPA), which consists of an in-phase PA (I-PA) and a quadrature PA (Q-PA), is controlled by the digital codewords based on an input signal to turn on and off the power cells inside the I-PA or the Q-PA. Due to the load interaction between the I-PA and the Q-PA, a 2-dimensional (2-D) digital pre-distortion (DPD) is applied to linearize the DPA. The whole transmitter is implemented in 40 nm CMOS LP process and occupies a die area of 0.7 mm2. The all-digital quadrature transmitter can support 20 MHz, 40 MHz, and 80 MHz WiFi signals, Band 38 and Band 40 LTE signals with class 3 output power, and Bluetooth BDR, EDR2, and EDR3 signals. View full abstract»

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  • All-Pass Filter-Based 2-D IIR Filter-Enhanced Beamformers for AESA Receivers

    Page(s): 1331 - 1342
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    An active electronically scanned array (AESA) beamforming method that provides enhanced selectivity (interference rejection) for the same number of antennas compared to conventional delay-and-sum (DAS) beamforming is proposed. Conventional DAS 2-D transfer function is modified by introducing complex pole-manifolds based on recently proposed 2-D infinite impulse response (IIR) beam filters, at guaranteed stability. A continuous-time domain signal flow graph is proposed based on first order all-pass filters that eliminate the need of transmission line-based delays used in conventional DAS beamformers. Improved interference rejection is verified using closed-form signal processing models. For an array of 64 antennas, with desired signal direction of arrival (DOA) 10 ° and interference DOA -60° from array broadside, the proposed scheme shows an improvement in the signal-to-interference ratio (SIR) around 7 dB for the same number of antennas, compared to DAS beamforming. The improvement in interference rejection is observed for both uniform and non-uniform aperture weights in terms of side lobe performance. A feasibility study is presented on potential CMOS circuit implementation of the proposed AESA for a linear array of eight antennas and maximum operational frequency of 1 GHz. View full abstract»

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  • Analytical and Experimental Study of Wide Tuning Range mm-Wave CMOS LC-VCOs

    Page(s): 1343 - 1354
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    The unprecedented interest in high bandwidth applications in the mm-wave range has set off a wave of research exploring techniques that enable wide tuning range voltage-controlled oscillators (VCOs). Low frequency CMOS LC-VCOs ( <;10 GHz) have been well studied in the literature and several approaches have been developed to optimize their performance. However, there lie several interesting challenges in the mm-wave space, specifically close to the fT/fmax, that motivate the need for analyzing the tuning range and phase noise in mm-wave VCOs. This paper presents a detailed analysis of the ultimate performance bound in simultaneously achieving low phase noise and wide tuning range in CMOS VCOs. The analysis is conducted on a 130 nm CMOS process, and confirmed by measurement results on three VCOs at 26 GHz, 34 GHz and 40 GHz. Finally, the impact of CMOS technology scaling (from 130 nm down to 45 nm), on the achievable performance bounds is analyzed and presented. View full abstract»

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  • Two Polynomial FIR Filter Structures With Variable Fractional Delay and Phase Shift

    Page(s): 1355 - 1365
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    This paper introduces two polynomial finite-length impulse response (FIR) digital filter structures with simultaneously variable fractional delay (VFD) and phase shift (VPS). The structures are reconfigurable (adaptable) online without redesign and do not exhibit transients when the VFD and VPS parameters are altered. The structures can be viewed as generalizations of VFD structures in the sense that they offer a VPS in addition to the regular VFD. The overall filters are composed of a number of fixed subfilters and a few variable multipliers whose values are determined by the desired FD and PS values. A systematic design algorithm, based on iteratively reweighted ℓ1-norm minimization, is proposed. It generates fixed subfilters with many zero-valued coefficients, typically located in the impulse response tails. The paper considers two different structures, referred to as the basic structure and common-subfilters structure, and compares these proposals as well as the existing cascaded VFD and VPS structures, in terms of arithmetic complexity, delay, memory cost, and transients. In general, the common-subfilters structure is superior when all of these aspects are taken into account. Further, the paper shows and exemplifies that the VFDPS filters under consideration can be used for simultaneous resampling and frequency shift of signals. View full abstract»

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  • Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis

    Page(s): 1366 - 1375
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    Low-density parity-check (LDPC) codes are adopted in many applications due to their Shannon-limit approaching error-correcting performance. Nevertheless, belief-propagation (BP) based decoding of these codes suffers from the error-floor problem, i.e., an abrupt change in the slope of the error-rate curve that occurs at very low error rates. Recently, a new type of decoders termed finite alphabet iterative decoders (FAIDs) were introduced. The FAIDs use simple Boolean maps for variable node processing, and can surpass the BP-based decoders in the error floor region with very short word length. We restrict the scope of this paper to regular dv=3 LDPC codes on the BSC channel. This paper develops a low-complexity implementation architecture for the FAIDs by making use of their properties. Particularly, an innovative bit-serial check node unit is designed for the FAIDs, and a small-area variable node unit is proposed by exploiting the symmetry in the Boolean maps. Moreover, an optimized data scheduling scheme is proposed to increase the hardware utilization efficiency. From synthesis results, the proposed FAID implementation needs only 52% area to reach the same throughput as one of the most efficient standard Min-Sum decoders for an example (7807, 7177) LDPC code, while achieving better error-correcting performance in the error-floor region. Compared to an offset Min-Sum decoder with longer word length, the proposed design can achieve higher throughput with 45% area, and still leads to possible performance improvement in the error-floor region. View full abstract»

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  • Parallel Interleaver Design for a High Throughput HSPA + /LTE Multi-Standard Turbo Decoder

    Page(s): 1376 - 1389
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    To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA +/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm 2. When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards. View full abstract»

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  • Modular Structure of Compact Model for Memristive Devices

    Page(s): 1390 - 1399
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    A modular compact model for memristors which describes a wide range of memristive devices is presented. Its modular structure enables the modeling of various device behaviors by adopting different functions inside the comprising blocks. Rooted from the theoretical analysis on ideal memristors, the window function of the model is uniquely based on the constitutive relationship between charge and flux. This not only solves the stability issue from previously reported models, but also reveals that an equivalent charge-flux constitutive relationship can always be obtained from a variety of memristive devices. Simulations on three types of memristive devices demonstrate that the model is able to reflect common memristive device properties such as limited memristance switching range, linear/nonlinear memristance switching rate, threshold voltages for SET/RESET, nonlinear I-V characteristics, and device parameters with variations. View full abstract»

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  • Energy-Efficient Clocking Based on Resonant Switching for Low-Power Computation

    Page(s): 1400 - 1408
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    A mechanism for the reduction of dynamic energy dissipation based on energy recovery resonant switching in a computing circuit is described. The resonant circuit with controlled switches conserves energy by recovering 90% of energy that would be otherwise lost during logic state transitions. The new approach of incorporating an energy recovery storage capacitor in the resonant circuit helps to initialize the logic operation and moves the energy back and forth to the load capacitance. This energy-conserving approach preserves thermodynamic entropy, ideally preventing heat generation in the system. This proposed method is used for generating an energy-efficient “flat-topped” (quasi-trapezoidal) waveform, which is required to perform the low power digital logic computation, especially for clocking in the system applications. View full abstract»

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  • On the Effects of Mismatch on Quadrature Accuracy in Tapped-Capacitor Load Independent Quadrature LC-Oscillators

    Page(s): 1409 - 1415
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    This paper presents a study of quadrature phase error due to various systematic mismatches and loading effects on the oscillation frequency in a tapped-capacitor parallel coupled LC-tank oscillator. Vector based analysis is carried out to evaluate the general oscillating condition. Closed-form expressions for oscillation frequency and quadrature accuracy in the presence of loading are derived for the case of weak coupling. It is shown with rigorous analysis, for the first time, that the tapped-capacitor LC-tank oscillator exhibits oscillation frequency that is independent of loading conditions. The analysis clearly demonstrates that the effects of mismatch in tapped-capacitors on quadrature accuracy can be minimized by proper choice of coupling factor and shows that the error due to these tapped-capacitors is independent of the quality factor of the tank. Results from Spectre simulations are used to validate the analytical results. View full abstract»

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  • Design Procedure of Quasi-Class-E Power Amplifier for Low-Breakdown-Voltage Devices

    Page(s): 1416 - 1428
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    This paper presents new design procedure for a general class-E power amplifier, here referred to as quasi-class-E, with finite dc-feed inductance and switch on-resistance and variable duty cycle under variable voltage switching (VVS), and variable derivative voltage switching (VDS), taking into account the switch breakdown voltage. It is shown that for non-zero switch on-resistance in class-E power amplifier, zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions do not necessarily result in maximum efficiency. Hence, by assuming VVS and VDS, new design equations are derived. The new equations can be solved with a simple and fast numerical method in MATLAB. The theoretical results show efficiency improvement for quasi-class-E power amplifier compared to conventional designs. Circuit simulations confirm the validity of the theoretical results. View full abstract»

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  • A GPU-Accelerated Web-Based Synthesis Tool for CT Sigma-Delta Modulators

    Page(s): 1429 - 1441
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    This paper presents a design environment for continuous-time sigma-delta analog-to-digital converters for automatic coefficient scaling using a genetic algorithm. In order to provide an interactive design tool which enables the designer to transform and refine basic performance specifications into the desired, detailed high-level filter description, a short response time is mandatory. Previously published heuristic-search-based design tools have response times in the range of several ten minutes up to hours and are mostly not freely available. In contrast, the design environment presented in this paper provides results in less than a minute due the utilization of a fast simulation method implemented on a graphics card processor. Our hardware supported approach allows performing between 10 k and 67 k simulations and evaluations per second for internal model orders of one to eight, allowing to investigate millions of settings in less than a minute. View full abstract»

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  • LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency

    Page(s): 1442 - 1455
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    This paper analyses the use of bandpass continuous-time ΣΔ modulators with widely programmable notch frequency for the efficient digitization of radio-frequency signals in the next generation of software-defined-radio mobile systems. The modulator architectures under study are based on a fourth-order loop filter - implemented with two LC-based resonators - and a finite-impulsive-response feedback loop in order to increase their flexibility and degrees of freedom. Several topologies are studied, considering three different cases for the embedded digital-to-analog converter, namely: return-to-zero, non-return-to-zero and raised-cosine waveform. In all cases, a notch-aware synthesis methodology is presented, which takes into account the dependency of the loop-filter coefficients on the notch frequency and compensates for the dynamic range degradation due to the variation of the notch. The synthesized modulators are compared in terms of their sensitivity to main circuit error mechanisms and the estimated power consumption over a notch-frequency tuning range of 0.1fs to 0.4fs. Time-domain behavioral and macromodel electrical simulations validate this approach, demonstrating the feasibility of the presented methodology and architectures for the efficient and robust digitization of radio-frequency signals with a scalable resolution and programmable signal bandwidth. View full abstract»

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  • Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain

    Page(s): 1456 - 1464
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    Scaling down the supply voltage (Vdd) below the transistors threshold voltage (Vth) has become a very popular technique in designing Ultra-Low-Power circuits whose demand has dramatically increased in the last few years. Designing these kinds of circuit is still a challenge, especially when the latest advanced process technologies are employed. The well-known design methodology used in the typical super-threshold domain (Vdd > Vth) cannot be applied to the design of a sub-threshold circuit due to the different transistor current-voltage relationships that hold when Vdd <; Vth. For this reason, designers need supports suitable for the sub-threshold domain. This paper proposes a complete mathematical model able to predict the output behavior of a sub-threshold CMOS inverter. The model proposed here takes into account the effects of the transient variation of the transistor on-current during the gate switching. Moreover, for the first time, over/undershoot effects due to the input-to-output coupling capacitance are taken into account. The proposed model is formed by closed-form expressions able to predict the over/undershoot position, its amplitude and the inverter delay with great accuracy. Furthermore, it can be easily exploited in predicting the delay of cascading inverters, usually used to realize clock buffers. Under Process-Voltage-Temperature variations, the delay of a single inverter realized using a commercial CMOS 45 nm process technology is predicted with a maximum error lower than 16%. Even better results are obtained when the model is applied to inverter chains. View full abstract»

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  • A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops

    Page(s): 1465 - 1472
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    Clock gating is very useful for reducing the power consumed by digital systems. Three gating methods are known. The most popular is synthesis-based, deriving clock enabling signals based on the logic of the underlying system. It unfortunately leaves the majority of the clock pulses driving the flip-flops (FFs) redundant. A data-driven method stops most of those and yields higher power savings, but its implementation is complex and application dependent. A third method called auto-gated FFs (AGFF) is simple but yields relatively small power savings. This paper presents a novel method called Look-Ahead Clock Gating (LACG), which combines all the three. LACG computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. It avoids the tight timing constraints of AGFF and data-driven by allotting a full clock cycle for the computation of the enabling signals and their propagation. A closed-form model characterizing the power saving per FF is presented. It is based on data-to-clock toggling probabilities, capacitance parameters and FFs' fan-in. The model implies a breakeven curve, dividing the FFs space into two regions of positive and negative gating return on investment. While the majority of the FFs fall in the positive region and hence should be gated, those falling in the negative region should not. Experimentation on industry-scale data showed 22.6% reduction of the clock power, translated to 12.5% power reduction of the entire system. View full abstract»

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  • A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations

    Page(s): 1473 - 1484
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    Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing power supply voltage in scaled CMOS technologies. A seven-transistor (7T), an eight-transistor (8T), a nine-transistor (9T), and 3 conventional six-transistor (6T) memory circuits are characterized for layout area, data stability, write voltage margin, data access speed, active power consumption, idle mode leakage currents, and minimum power supply voltage in this paper. A comprehensive electrical performance metric is evaluated to compare the memory cells considering process parameter and supply voltage fluctuations. The triple-threshold-voltage 8T and 9T SRAM cells provide up to 2.5× stronger data stability and 765.9× higher overall electrical quality as compared to the traditional 6T SRAM cells in a TSMC 65 nm CMOS technology. View full abstract»

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  • Fusion Estimation for Sensor Networks With Nonuniform Estimation Rates

    Page(s): 1485 - 1498
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    This paper investigates the multi-sensor fusion estimation problem for wireless sensor networks with nonuniform estimation rates. First, each sensor generates local estimates with two rates, namely, a fast rate and a slow rate according to its power situation, where the estimation rates among the sensors are allowed to be different from each other. Second, a fusion rule with matrix weights is designed for each sensor to fuse available local estimates generated at different time scales, and a set of recursive equations are presented to compute estimation error cross-covariances. The fusion algorithm is applicable to both cases where the measurement noises are mutually correlated and are uncorrelated, and is also applicable to the case where the sensors are not time-synchronized. Two types of estimators are designed according to different considerations of design complexity and computation costs, and convergence analysis for the type II estimators is also presented. Finally, two illustrative examples are given to demonstrate the effectiveness of the proposed estimators. View full abstract»

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  • Sparse Adaptive Filtering by an Adaptive Convex Combination of the LMS and the ZA-LMS Algorithms

    Page(s): 1499 - 1507
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    In practice, one often encounters systems that have a sparse impulse response, with the degree of sparseness varying over time. This paper presents a new approach to identify such systems which adapts dynamically to the sparseness level of the system and thus works well both in sparse and non-sparse environments. The proposed scheme uses an adaptive convex combination of the LMS algorithm and the recently proposed, sparsity-aware zero-attractor LMS (ZA-LMS) algorithm. It is shown that while for non-sparse systems, the proposed combined filter always converges to the LMS algorithm (which is better of the two filters for non-sparse case in terms of lesser steady state excess mean square error (EMSE)), for semi-sparse systems, on the other hand, it actually converges to a solution that produces lesser steady state EMSE than produced by either of the component filters. For highly sparse systems, depending on the value of a proportionality constant in the ZA-LMS algorithm, the proposed combined filter may either converge to the ZA-LMS based filter or may produce a solution which, like the semi-sparse case, outperforms both the constituent filters. A simplified update formula for the mixing parameter of the adaptive convex combination is also presented. The proposed algorithm requires much less complexity than the existing algorithms and its claimed robustness against variable sparsity is well supported by simulation results. View full abstract»

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  • Distributed Robust Synchronization of Dynamical Networks With Stochastic Coupling

    Page(s): 1508 - 1519
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    This paper deals with the problem of robust adaptive synchronization of dynamical networks with stochastic coupling by means of evolutionary algorithms. The complex networks under consideration are subject to: 1) the coupling term in a stochastic way is considered; 2) uncertainties exist in the node's dynamics; and 3) pinning distributed synchronization is also considered. By resorting to Lyapunov function methods and stochastic analysis techniques, the tasks to get the distributed robust synchronization and distributed robust pinning synchronization of dynamical networks are solved in terms of a set of inequalities, respectively. The impacts of degree information, stochastic coupling, and uncertainties on synchronization performance, i.e., mean control gain and convergence rate, are derived theoretically. The potential conservativeness for the distributed robust pinning synchronization problem is solved by means of an evolutionary algorithm-based optimization method, which includes a constraint optimization evolutionary algorithm and a convex optimization method and aims at improving the traditional optimization methods. Simulations are provided to illustrate the effectiveness and applicability of the obtained results. View full abstract»

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  • Coupling Strength Allocation for Synchronization in Complex Networks Using Spectral Graph Theory

    Page(s): 1520 - 1530
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    Using spectral graph theory and especially its graph comparison techniques, we propose new methodologies to allocate coupling strengths to guarantee global complete synchronization in complex networks. The key step is that all the eigenvalues of the Laplacian matrix associated with a given network can be estimated by utilizing flexibly topological features of the network. The proposed methodologies enable the construction of different coupling-strength combinations in response to different knowledge about subnetworks. Adaptive allocation strategies can be carried out as well using only local network topological information. Besides formal analysis, we use simulation examples to demonstrate how to apply the methodologies to typical complex networks. View full abstract»

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  • Guaranteed-Cost Consensus for Singular Multi-Agent Systems With Switching Topologies

    Page(s): 1531 - 1542
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    Guaranteed-cost consensus problems for high-order singular multi-agent systems with switching topologies are investigated. Firstly, to achieve a trade-off design object between consensus regulation performances and control energy consumptions, a quadratic cost function is constructed by state errors among agents and control inputs of all agents and guaranteed-cost consensus problems are introduced. Then, based on linear matrix inequality techniques, sufficient conditions for guaranteed-cost consensus and consensualization are presented respectively, which can guarantee the scalability of singular multi-agent systems since the dimensions of all the variables in these conditions are independent of the number of agents. Moreover, an upper bound of the cost function is determined, explicit expressions of consensus functions are given on the basis of the Second Equivalent Form, and it is shown that consensus functions are dependent on the average of initial states of all agents but are independent of switching topologies. Finally, the applications of theoretical results in multi-agent supporting systems are shown. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras