# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 32

Publication Year: 2014, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2014, Page(s): C2
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• ### Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention

Publication Year: 2014, Page(s):957 - 970
Cited by:  Papers (9)
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This paper explores the design of 3-D-integrated hybrid memory by conductive-bridge random-access-memory (CBRAM). Considering internal states, height, and radius of the conductive bridge of one CBRAM device, an accurate CBRAM device model is developed for CBRAM-crossbar-based nonvolatile memory design with efficient estimation of area, access time, and power. Based on this design platform, one 3-D... View full abstract»

• ### Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline

Publication Year: 2014, Page(s):971 - 982
Cited by:  Papers (9)  |  Patents (1)
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This paper presents a new average-8T write/read decoupled (A8T-WRD) SRAM architecture for low-power sub/near-threshold SRAM in power-constraint applications such as biomedical implants and autonomous sensor nodes. The proposed architecture consists of several novel concepts in dealing with issues in sub/near-threshold SRAM including: 1) the differential and data-independent-leakage read port that ... View full abstract»

• ### On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time

Publication Year: 2014, Page(s):983 - 994
Cited by:  Papers (10)
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The coarse-grained reconfigurable architecture (CGRA) is proven to be energy efficient in several specific domains. In CGRAs, the on-chip memory hierarchy, which contains the context memory and the data memory organizations, should be well considered to achieve appropriate tradeoffs among three aspects: 1) performance; 2) area; and 3) power. In this paper, two techniques called the hierarchical co... View full abstract»

• ### Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over ${rm GF}(2^{m})$

Publication Year: 2014, Page(s):995 - 1003
Cited by:  Papers (9)
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The extended Euclidean algorithm (EEA) is an important scheme for performing the division operation in finite fields. Many sensitive and security-constrained applications such as those using the elliptic curve cryptography for establishing key agreement schemes, augmented encryption approaches, and digital signature algorithms utilize this operation in their structures. Although much study is perf... View full abstract»

• ### Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory

Publication Year: 2014, Page(s):1004 - 1015
Cited by:  Papers (23)
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The reliability of data stored in high-density Flash memory devices tends to decrease rapidly because of the reduced cell size and multilevel cell technology. Soft-decision error correction algorithms that use multiple-precision sensing for reading memory can solve this problem; however, they require very complex hardware for high-throughput decoding. In this paper, we present a rate-0.96 (68254, ... View full abstract»

• ### Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs

Publication Year: 2014, Page(s):1016 - 1029
Cited by:  Papers (8)
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The counterfeiting and recycling of integrated circuits (ICs) have become major issues in recent years, potentially impacting the security and reliability of electronic systems bound for military, financial, or other critical applications. With identical functionality and packaging, it would be extremely difficult to distinguish recycled ICs from unused ICs. In this paper, two types of on-chip lig... View full abstract»

• ### Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits

Publication Year: 2014, Page(s):1030 - 1041
Cited by:  Papers (4)
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Noise such as voltage drop and temperature in integrated circuits can cause significant performance variation and even functional failure in lower technology nodes. In this paper, we propose a lightweight on-chip structure that measures timing uncertainty induced by noise during functional and test operations. The proposed on-chip structure, facilitates speed characterization under various workloa... View full abstract»

• ### Logical Effort for CMOS-Based Dual Mode Logic Gates

Publication Year: 2014, Page(s):1042 - 1053
Cited by:  Papers (6)
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Recently, a novel dual mode logic (DML) family was proposed. This logic allows operation in two modes: 1) static and 2) dynamic modes. DML gates, which can be switched between these modes on-the-fly, feature very low power dissipation in the static mode and high performance in the dynamic mode. A basic DML gate is very simple and is composed of any static logic family gate and an additional clocke... View full abstract»

• ### Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method

Publication Year: 2014, Page(s):1054 - 1059
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This paper presents a hardware architecture for efficient implementation of the well equidistributed long-period linear (WELL) algorithm. Our design achieves a throughput of one sample-per-cycle and runs as fast as 423 MHz on a Xilinx XC5VFX130T field-programmable gate array (FPGA) device. This performance is 7.1-fold faster than a dedicated software implementation. The proposed architecture is al... View full abstract»

• ### Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority

Publication Year: 2014, Page(s):1060 - 1068
Cited by:  Papers (13)
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This paper presents a low-power coordinate rotation digital computer (CORDIC)-based reconfigurable discrete cosine transform (DCT) architecture. The main idea of this paper is based on the interesting fact that all the computations in DCT are not equally important in generating the frequency domain outputs. Considering the importance difference in the DCT coefficients, the number of CORDIC iterati... View full abstract»

• ### Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer

Publication Year: 2014, Page(s):1069 - 1081
Cited by:  Papers (1)
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This paper presents a novel framework to efficiently and effectively build a robust but routing-friendly multilayer power network under the IR-drop and electro-migration (EM) constraints. The proposed framework first considers the impact of the aluminum-pad layer and provides a conservative analytical model to determine the total metal width for each power layer that can meet the IR-drop and EM co... View full abstract»

• ### UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

Publication Year: 2014, Page(s):1082 - 1095
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As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processing cores. Traditionally, to maximize design flexibility, interchip and intrachip communication architectures are separately designed under different constraints. Jointly designing communication architectures for both interc... View full abstract»

• ### High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

Publication Year: 2014, Page(s):1096 - 1105
Cited by:  Papers (7)
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In high-speed data transmission applications, such as double data rate memory and double sampling analog-to-digital converter, the positive and negative edges of the system clock are utilized for data sampling. Thus, these systems require an exact 50% duty cycle of the system clock. In this paper, two wide-range all-digital duty-cycle correctors (ADDCCs) with output clock phase alignment are prese... View full abstract»

• ### Variation-Aware Variable Latency Design

Publication Year: 2014, Page(s):1106 - 1117
Cited by:  Papers (3)
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Although typical digital circuits are designed so that the clock period satisfies worst case path delay constraints, the average input excitation often completes computation in less than a clock cycle. Variable latency units (VLUs) allow for improved throughput by allowing one clock cycle for some computations, and two clock cycles for others, using hold logic to differentiate between the two case... View full abstract»

• ### 1.9-ps Jitter, 10.0-dBm-EMI Reduction Spread-Spectrum Clock Generator With Autocalibration VCO Technique for Serial-ATA Application

Publication Year: 2014, Page(s):1118 - 1126
Cited by:  Papers (4)
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A spread-spectrum clock generator (SSCG) that is characterized by a low jitter voltage-controlled oscillator (VCO) with a high-frequency limiter and an autocalibration function is developed for a Serial-ATA application. The high-frequency limiter prevents the SSCG from going into an unlocked state. The proposed VCO achieved far less jitter than a conventional one because a proposed structure has f... View full abstract»

• ### A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals

Publication Year: 2014, Page(s):1127 - 1137
Cited by:  Papers (1)
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This paper presents a 12.5-Gb/s on-chip oscilloscope (OCO) circuit to measure eye diagrams and jitter histograms of high-speed digital signals. The proposed circuit adopts a novel architecture to capture both single-ended and differential signals. In addition, it is capable of measuring the eye openings and jitter of the input signals without the need to construct the whole eye diagram which makes... View full abstract»

• ### Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization

Publication Year: 2014, Page(s):1138 - 1149
Cited by:  Papers (2)
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As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layout-dependent effects (LDE) for validation ... View full abstract»

• ### FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

Publication Year: 2014, Page(s):1150 - 1163
Cited by:  Papers (10)
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Recently, FinFETs have emerged as promising substitutes for conventional CMOS because of their superior control of short-channel effects and processing scalability. Nevertheless, lithographic constraints, difficulties in workfunction engineering, supply voltage variations, and temperature nonuniformity across the FinFET integrated circuit may lead to process, supply voltage, and temperature (PVT) ... View full abstract»

• ### 1-V 365- $\mu{\rm W}$ 2.5-MHz Channel Selection Filter for 3G Wireless Receiver in 55-nm CMOS

Publication Year: 2014, Page(s):1164 - 1169
Cited by:  Papers (3)
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This paper presents a novel 1-V 2.5-MHz continuous-time filter for 3G wireless application, fabricated using a standard 55-nm CMOS process. The four-pole filter topology includes a single pole-tracking Operational Amplifier (OPAMP) structure to achieve low in-band noise levels, high out-of-band linearity, and reduced power consumption. An automatic frequency tuning circuit is developed to compensa... View full abstract»

• ### Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning

Publication Year: 2014, Page(s):1170 - 1174
Cited by:  Papers (1)
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Multiple patterning lithography is the most likely manufacturing process for sub-32 nm technology nodes. Among different multiple patterning methods, self-aligned patterning has attracted much interest due to its robustness against overlay errors. However, self-aligned patterning compliance is subject to the litho-friendliness of the applied decomposition method. This brief establishes self-aligne... View full abstract»

• ### Area-Delay Efficient Binary Adders in QCA

Publication Year: 2014, Page(s):1174 - 1179
Cited by:  Papers (18)
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As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always stra... View full abstract»

• ### Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM

Publication Year: 2014, Page(s):1179 - 1182
Cited by:  Papers (7)  |  Patents (1)
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Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is an emerging type of nonvolatile memory with compelling advantages in endurability, scalability, speed, and energy consumption. As the process technology shrinks, STT-MRAM has limited sensing margin due to the decrease in supply voltage and increase in process variation. Furthermore, the relatively smaller resistance differenc... View full abstract»

• ### High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

Publication Year: 2014, Page(s):1183 - 1187
Cited by:  Papers (6)
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This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed t... View full abstract»

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu