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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 4 • Date April 2014

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Displaying Results 1 - 25 of 34
  • Table of Contents

    Publication Year: 2014 , Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Publication Year: 2014 , Page(s): C2
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  • Digital Systems Power Management for High Performance Mixed Signal Platforms

    Publication Year: 2014 , Page(s): 961 - 975
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    High performance mixed signal (HPMS) platforms require stringent overall system and subsystem performance. The ability to design ultra-low power systems is used in a wide range of platforms including consumer, mobile, identification, healthcare products and microcontrollers. In this paper we present an overview of low power design techniques, challenges and opportunities faced in an industrial research environment. The paper presents strategies on the deployment of low power techniques that span from power-performance optimization scenarios accounting for active and standby operation modes to the development of multi-core architectures suitable for low voltage operation. View full abstract»

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  • Analysis and Design of Class- {\rm E}_{\rm M} Power Amplifier

    Publication Year: 2014 , Page(s): 976 - 986
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    This paper presents analytical expressions for the class-EM power amplifier, taking into account the fundamental-frequency and harmonic components of output currents in the main and auxiliary circuits. By using the proposed expressions, design values for satisfying not only the class-EM ZVS/ZDVS/ZCS/ZDCS conditions of the main circuit, but also the ZVS condition of the auxiliary circuit can be achieved without applying any tuning process. The analytical predictions agreed with experimental and PSpice-simulation results quantitatively, which showed the validity of analytical expressions given in this paper. View full abstract»

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  • Modeling and Analysis of Class-E Amplifier With a Shunt Inductor at Sub-Nominal Operation for Any Duty Ratio

    Publication Year: 2014 , Page(s): 987 - 1000
    Cited by:  Papers (1)
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    This paper presents analytical expressions for the sub-nominal operation, which is only the zero current switching (ZCS) condition, of the class-E power amplifier with a shunt inductor at any duty ratio. The duty ratio is considered not only as a design specification but also as an adjustment parameter. In the sub-nominal operation with any duty ratio, both the peak switch voltage and the peak switch current can be set as design specifications due to two more degrees of design freedom in comparison with the class-E nominal amplifier at the fixed duty ratio. Additionally, it is also seen that the duty ratio affects the maximum operating frequency and the output power capability with ZCS condition. A design example of the class-E ZCS amplifier with a shunt inductor under the specifications of peak switch voltage and peak switch current is given. The measurement and a simulation by circuit simulator results agreed with the analytical expressions quantitatively, which show the validity of our analytical expressions. View full abstract»

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  • A 5-Gb/s Serial-Link Redriver With Adaptive Equalizer and Transmitter Swing Enhancement

    Publication Year: 2014 , Page(s): 1001 - 1011
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    A single-lane, dual-channel, 5-Gb/s serial link redriver with no clock data recovery (CDR) or phase-locked loop (PLL) has been developed by using a standard 0.13- μm CMOS technology. New features and techniques have been developed in both the architecture and the analog modules to meet the jitter and protocol requirements for a redriver for multi-Gb/s operation, which is made difficult by the lack of CDR and a PLL. These techniques include: 1) adaptive receiver equalization; 2) enhanced transmitter output swing and programmable de-emphasis/swing settings; 3) a robust state flow control combined with various signal detectors to provide automatic state and mode switching without affecting operations of upstream and downstream ports. The redriver chip consumes 165 mA in 5 Gb/s bidirectional full-duplex operation from a single 3.3 V power supply. View full abstract»

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  • Architecture of a Single-Chip 50 Gb/s DP-QPSK/BPSK Transceiver With Electronic Dispersion Compensation for Coherent Optical Channels

    Publication Year: 2014 , Page(s): 1012 - 1025
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1879 KB) |  | HTML iconHTML  

    The architecture of a single-chip dual-polarization QPSK/BPSK 50 Gigabits per second (Gb/s) DSP-based transceiver for coherent optical communications is presented. The receiver compensates the chromatic dispersion (CD) of more than 3,500 km of standard single-mode fiber using a frequency-domain equalizer. A time-domain four-dimensional MIMO transversal equalizer compensates up to 200 ps of differential group delay (DGD) and 8000 ps 2 of second-order polarization-mode dispersion (SOPMD). Other key DSP functions of the receiver include carrier and timing recovery, automatic gain control, channel diagnostics, etc. A novel low-latency parallel-processing carrier recovery implementation which is robust in the presence of laser phase noise and frequency jitter is proposed. The chip integrates the transmitter, receiver, framer and host interface functions and features a 4-channel 25 Gs/s 6-bit ADC with a figure of merit (FOM) of 0.4 pJ/conversion. Each ADC channel is based on an 8-way interleaved flash architecture. The DSP uses a 16-way parallel processing architecture. Extensive measurement results are presented which confirm the design targets. Measured optical signal-to-noise ratio (OSNR) penalty when compensating 200 ps DGD and 8000 ps 2 is 0.1 dB, while OSNR penalty when compensating 55 ns/nm CD (corresponding to 3,500 km of standard single-mode fiber) is 0.5 dB. View full abstract»

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  • A Novel 1.2–V 4.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference

    Publication Year: 2014 , Page(s): 1026 - 1035
    Cited by:  Papers (1)
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    This paper proposes a novel CMOS bandgap reference (BGR) with high-order curvature-compensation by using MOS transistors operating in weak inversion region. The mechanism of the proposed curvature-compensation technique is analyzed thoroughly and the corresponding BGR circuit was implemented in standard CMOS 0.18 μm technology. The experimental results show that the proposed BGR achieves 4.5 ppm/°C over the temperature range of -40°C to 120°C at 1.2 V supply voltage. It consumes only 36 μA. In addition, it achieves line regulation performance of 0.054%/V. It is suitable for low-power applications requiring references with high precision. View full abstract»

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  • Ambient Light Organic Sensor in a Printed Complementary Organic TFT Technology on Flexible Plastic Foil

    Publication Year: 2014 , Page(s): 1036 - 1043
    Cited by:  Papers (1)
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    This paper presents an organic sensor for ambient light monitoring fabricated on flexible plastic foil. The sensor exploits an organic photodiode whose photocurrent is linearly converted into an output voltage by a transconductance operational amplifier in a feedback configuration. The photodiode is based on an inkjet printed bulk heterojunction blend of P3HT/PCBM sandwiched between Au and Al electrodes, whereas the amplifier is implemented in a printed complementary organic TFT technology. Both the photodiode and the amplifier were fully characterized in stand-alone configuration. Then, the response of the assembled sensor was measured by using a commercial 12-V halogen lamp as light source. Experimental data demonstrated that the sensor is able to provide a linear detection of the incident light intensity up to 11000 lux. View full abstract»

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  • A Study of Deterministic Jitter in Crystal Oscillators

    Publication Year: 2014 , Page(s): 1044 - 1054
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    Crystal oscillators are widely used in electronic systems to provide reference timing signals. Even though they are designed to be highly stable, their performance can be deteriorated by several types of random noise sources and deterministic interferences. This paper investigates the phenomenon of timing jitter in crystal oscillators induced by the injection of deterministic interferences. It is shown that timing jitter is closely related to the phase and amplitude modulations of the oscillator response. A closed-form variational macromodel is proposed to quantify timing jitter as well as to qualitatively explain the interference mechanism. Analytical results and efficient numerical simulations are developed to explore how timing jitter depends on the frequency of the interfering signal. The methodology is tested by a crystal Pierce oscillator. View full abstract»

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  • High Precision Synthesis of a Richards Immittance Via Parametric Approach

    Publication Year: 2014 , Page(s): 1055 - 1067
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    A Richards immitance is a positive real function expressed in terms of the Richards variable λ = tanh(pτ) = Σ+jΩ where p=σ+jω is the classical complex frequency. A Richards immittance can be synthesized as a lossless two port terminated in a resistance as in Darlington's synthesis such that the two-port consists of commensurate transmission lines. In this paper, a high precision method is presented to synthesize a Richards immittance as a lossless two-port constructed with cascade connections of equal length transmission lines, as well as short and open stubs. The new method of synthesis utilizes Bode procedure (or Parametric Method) to correct an immitance function specified in the complex Richards variable λ at each step of the synthesis. It is verified that new technique can synthesize a randomly generated Richards immitance function yielding 25 commensurate lines with the accumulated numerical error less than 10-3. A complete synthesis package is developed in MatLab and successfully integrated with the Real Frequency Technique to design broadband matching networks. Examples are presented to show the merits of the new Richards synthesis tool. View full abstract»

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  • A 10-Gb/s, 107-mW Double-Edge Pulsewidth Modulation Transceiver

    Publication Year: 2014 , Page(s): 1068 - 1080
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    A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation to overcome frequency-dependent losses in electrical interconnects. Time domain modulation is discussed as a means to enhance the spectral efficiency in channels with sharp frequency roll-off similar to multilevel voltage-domain modulation such as 4-PAM. The transmitter and receiver are high-speed programmable digital-to-time and time-to-digital converters that adapt to channel bandwidth characteristics with a timing resolution of 40 ps. This paper presents a low-jitter, phase rotation architecture for cycle-to-cycle transmit pulsewidth control. The transceiver includes an elastic buffer to move data between synchronous and plesiochronous clock domains and is implemented in 45-nm CMOS SOI. Transmitter and receiver functionality is demonstrated to 10 Gb/s at a BER of under 10-12 and is compared against NRZ schemes at the same rate. The inductor-less transmitter and receiver active circuitry respectively occupy an area of 93 × 94 and 218 × 160 μm2, and consume a total 107 mW from a 1.2 V supply. View full abstract»

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  • A 16-Core Processor With Shared-Memory and Message-Passing Communications

    Publication Year: 2014 , Page(s): 1081 - 1094
    Cited by:  Papers (1)
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    A 16-core processor with both message-passing and shared-memory inter-core communication mechanisms is implemented in 65 nm CMOS. Message-passing communication is enabled in a 3 × 6 Mesh packet-switched network-on-chip, and shared-memory communication is supported using the shared memory within each cluster. The processor occupies 9.1 mm2 and operates fully functional at a clock rate of 750 MHz at 1.2 V and maximum 800 MHz at 1.3 V. Each core dissipates 34 mW under typical conditions at 750 MHz and 1.2 V while executing embedded applications such as an LDPC decoder, a 3780-point FFT module, an H.264 decoder and an LTE channel estimator. View full abstract»

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  • Selective State Retention Power Gating Based on Gate-Level Analysis

    Publication Year: 2014 , Page(s): 1095 - 1104
    Cited by:  Papers (1)
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    This work presents a novel approach based on gate-level analysis for implementing Selective State Retention Power Gating (SSRPG). A selective SRPG approach mitigates the area and power overhead of the conventional SRPG technique. However, only very few papers suggesting a selective SPRG approach were published. The proposed SSRPG technique employs a formal analysis and, therefore, does not require exhaustive simulations. To implement the new approach, an automatic algorithm, which is performed on a gate-level netlist, has been developed. This algorithm enables the extraction of a subset of flip-flops that is sufficient for a proper state retention power gating. Unique selective SRPG criteria have been defined to support the proposed algorithm. These criteria are used to reduce the total amount of the required retention cells. To the best of our knowledge, this is the first robust SSRPG approach using gate-level analysis for selecting a reduced sub set of FFs that require retention. The proposed approach has been applied to a practical design with about 3300 FFs. The experimental results show 78% reduction of the retention SPRG cell area overhead, compared to the common SRPG approach. View full abstract»

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  • A 0.6–107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG

    Publication Year: 2014 , Page(s): 1105 - 1118
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    Compressive sensing has been used to overcome communication constraints (energy and bandwidth) in low-power sensors. In this work, we present a seizure-detection processor that directly uses compressively-sensed electroencephalograms (EEGs) for embedded signal analysis. In addition to addressing communication, this has two advantages for local computation. First, with compressive sensing, reconstruction costs are typically severe, precluding embedded analysis; directly analyzing the compressed signals circumvents reconstruction costs, enabling embedded analysis within applications. Second, compared to Nyquist-sampled signals, the use of compressed representations reduces the computational energy of signal analysis due to the reduced number of signal samples. We describe an algorithmic formulation as well as a hardware architecture that enables two strong power-management knobs, wherein application-level performance can scale with computational energy. The two knobs are parameterized as follows: 1) ξ, which quantifies the amount of data compression, and 2) ν, which determines the approximation error within the proposed compressed-domain processing algorithm. For ξ and ν in the range 2-24×, the energy to extract signal features (over 18 channels) is 70.8-1.3 nJ, and the detector's performance for sensitivity, latency, and specificity is 96-91%, 4.7-5.3 sec., and 0.17-0.30 false-alarms/hr., respectively (compared to a baseline performance of 96%, 4.6 sec., and 0.15 false-alarms/hr.). View full abstract»

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  • NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture

    Publication Year: 2014 , Page(s): 1119 - 1132
    Cited by:  Papers (2)
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    The proposed unified solid-state storage (USSS) with hybrid NAND flash memory/ReRAM provides high system-level data protection. In the conventional storage system, the hierarchical storage architecture (Server/Disk array/SSD/NAND flash memory) has duplicated functions. USSS solves this structural problem of the conventional enterprise-storage systems. The proposed unified storage controller integrates the duplicated functions (error corrections and redundancies). Five highly reliable techniques are presented; reverse-mirroring (RM), shift-mirroring (SM), error-reduction synthesis (ERS), page-RAID, and error-masking (EM). SM is a modified technique from RM with no ReRAM buffer. These technologies utilize error-patterns asymmetries of the NAND flash memory and fast, page-rewritable and high endurance ReRAM. RM, SM and EM are the mirroring techniques to reduce bit-errors of the NAND flash memory by intelligently allocating the write address and comparing the data in the primary/mirrored NAND flash memories, respectively. The page-RAID generates the block-parity in each block and EM records the error-location during read. Without mirroring, the acceptable raw BER of the NAND flash memory (ABER) increases by 4.4×. Moreover, when RM, ERS, page-RAID, and EM are applied, the ABER increases by 32×. This corresponds to an increase of the endurance or the data-retention time of the NAND flash memory by 4.2 or 34×. View full abstract»

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  • An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

    Publication Year: 2014 , Page(s): 1133 - 1143
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    Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. In this work, we focus on optimizing the design of the fused Add-Multiply (FAM) operator for increasing performance. We investigate techniques to implement the direct recoding of the sum of two numbers in its Modified Booth (MB) form. We introduce a structured and efficient recoding technique and explore three different schemes by incorporating them in FAM designs. Comparing them with the FAM designs which use existing recoding schemes, the proposed technique yields considerable reductions in terms of critical delay, hardware complexity and power consumption of the FAM unit. View full abstract»

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  • Efficient Algorithm and Architecture for Elliptic Curve Cryptography for Extremely Constrained Secure Applications

    Publication Year: 2014 , Page(s): 1144 - 1155
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2011 KB) |  | HTML iconHTML  

    Recently, considerable research has been performed in cryptography and security to optimize the area, power, timing, and energy needed for the point multiplication operations over binary elliptic curves. In this paper, we propose an efficient implementation of point multiplication on Koblitz curves targeting extremely-constrained, secure applications. We utilize the Gaussian normal basis (GNB) representation of field elements over GF(2m) and employ an efficient bit-level GNB multiplier. One advantage of this GNB multiplier is that we are able to reduce the hardware complexity through sharing the addition/accumulation with other field additions. We utilized the special property of normal basis representation and squarings are implemented very efficiently by only rewiring in hardware. We introduce a new technique for point addition in affine coordinate which requires fewer registers. Based on this technique, we propose an extremely small processor architecture for point multiplication. Through application-specific integrated circuit (ASIC) implementations, we evaluate the area, performance, and energy consumption of the proposed crypto-processor. Utilizing two different working frequencies, it is shown that the proposed architecture reaches better results compared to the previous works, making it suitable for extremely-constrained, secure environments. View full abstract»

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  • Multifunction Residue Architectures for Cryptography

    Publication Year: 2014 , Page(s): 1156 - 1169
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    A design methodology for incorporating Residue Number System (RNS) and Polynomial Residue Number System (PRNS) in Montgomery modular multiplication in GF(p) or GF(2n) respectively, as well as a VLSI architecture of a dual-field residue arithmetic Montgomery multiplier are presented in this paper. An analysis of input/output conversions to/from residue representation, along with the proposed residue Montgomery multiplication algorithm, reveals common multiply-accumulate data paths both between the converters and between the two residue representations. A versatile architecture is derived that supports all operations of Montgomery multiplication in GF(p) and GF(2n), input/output conversions, Mixed Radix Conversion (MRC) for integers and polynomials, dual-field modular exponentiation and inversion in the same hardware. Detailed comparisons with state-of-the-art implementations prove the potential of residue arithmetic exploitation in dual-field modular multiplication. View full abstract»

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  • A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High Throughput VLSI Implementation

    Publication Year: 2014 , Page(s): 1170 - 1182
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3379 KB) |  | HTML iconHTML  

    Geometric Mean Decomposition (GMD) is considered an efficient precoding scheme in joint MIMO transceiver designs capable of facilitating asymptotically equivalent performance of maximum likelihood detector (MLD). In this paper, a low complexity and non-iterative GMD computing scheme featuring a divide-and-conquer approach is presented. It requires no iterative singular value decomposition (SVD) as pre-processing and is thus exempted from the convergence problem adverse to a constant throughput hardware implementation. The divide-and-conquer approach reduces the computing complexity and provides abundant computing parallelism. The basic operation of the proposed scheme is a real valued Givens rotation, which can be efficiently implemented using CORDIC algorithm. Computing complexity analyses indicate that the proposed scheme is at least 30% more computing efficient than other SVD based GMD computing schemes. Finally, a unified GMD/QRD design using a fully parallel and deeply pipelined architecture is presented. One GMD or QRD computation on a 4x4 complex-valued matrix can be accomplished every 4 clock cycles. Chip implementation in TSMC 90 nm CMOS technology shows that, with a maximum clock frequency up to 170 MHz, the design can perform 42.5 M GMD computations per second. The equivalent data rate is 1.02 Gbps for a 64 QAM modulation scheme. View full abstract»

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  • Fuzzy Modelling and Consensus of Nonlinear Multiagent Systems With Variable Structure

    Publication Year: 2014 , Page(s): 1183 - 1191
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    The consensus problem of multiagent nonlinear systems (MANNs) with variable structure is discussed in this paper. T-S fuzzy models are first presented to describe MANNs with variable structure. The nodes of each T-S fuzzy model are rearranged so that the global fuzzy model is decomposed into independent and small-scale fuzzy models. It is shown that the consensus of the global fuzzy model is equivalent to that of its corresponding small-scale fuzzy models in which the continuous and sampled controllers are applied. Sufficient conditions are derived to ensure the consensus of the controlled fuzzy models. Finally, simulation results are given to illustrate the effectiveness of the proposed criteria. View full abstract»

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  • Design-Oriented Analysis of Quantization-Induced Limit Cycles in a Multiple-Sampled Digitally Controlled Buck Converter

    Publication Year: 2014 , Page(s): 1192 - 1205
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    Digital control of switching power converters is an area which has seen increased attention in recent years. However, quantization in the feedback loop from the analog-to-digital (A/D) converter and the digital pulse width modulator (DPWM) may cause limit cycle oscillations to manifest, which are generally seen as being undesirable. This paper presents an analysis of the limit cycle behavior found in a multiple-sampled digitally controlled buck converter. The limit cycles which may arise in the system are characterized and conditions to prevent these oscillations from occurring are presented. View full abstract»

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  • Digital Multiplierless Implementation of Biological Adaptive-Exponential Neuron Model

    Publication Year: 2014 , Page(s): 1206 - 1219
    Cited by:  Papers (1)
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    High-accuracy implementation of biological neural networks is a computationally expensive task, specially, for large-scale simulations of neuromorphic algorithms. This paper proposes a set of models for biological spiking neurons, which are efficiently implementable on digital platforms. Proposed models can reproduce different biological behaviors with a high precision. The proposed models are investigated, in terms of digital implementation feasibility and costs, targeting low-cost hardware implementation. Hardware synthesis and physical implementations on a field-programmable gate array show that the proposed models can produce biological behavior of different types of neurons with higher performance and considerably lower implementation costs compared with the original model. View full abstract»

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  • Synchronization of Nonlinear Dynamical Networks With Heterogeneous Impulses

    Publication Year: 2014 , Page(s): 1220 - 1228
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    In this paper, the synchronization problem is investigated for a class of nonlinear delayed dynamical networks with heterogeneous impulsive effects. The intrinsic properties of heterogeneous impulses are that impulsive strengths are inhomogeneous in both time and space domains, i.e., the impulsive effect in each node is not only nonidentical from each other, but also time-varying at different impulsive instants. The purpose of the addressed problem is to derive synchronization criteria such that, the nonlinear delayed dynamical networks with heterogeneous impulses can be synchronized to a desired state. By means of a time-dependent Lyapunov function and the comparison principle, several sufficient conditions are established under which nonlinear dynamical networks with heterogeneous impulsive effects are exponentially synchronized to a desired state. An example is given to show the effectiveness of the proposed results. View full abstract»

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  • Electronically Tunable Doherty Power Amplifier for Multi-Mode Multi-Band Base Stations

    Publication Year: 2014 , Page(s): 1229 - 1240
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2370 KB) |  | HTML iconHTML  

    This paper proposes an electronically reconfigurable Doherty amplifier capable of efficiently amplifying multi-standard multi-band wireless signals centered at widely spaced frequencies. The paper outlines closed form equations for an effective design methodology of frequency agile Doherty amplifiers driven with multi-mode signals using a small number of electronically tunable devices. As a proof of concept, a reconfigurable Doherty prototype is designed and fabricated to operate at 1.9, 2.14, and 2.6 GHz meant to efficiently amplify signals with peak-to-average power ratio equal to 6, 9 and 12 dB. The measurement results obtained using continuous wave signals reveal drain efficiencies of about 67% and 42% at the peak power and 12 dB output back off power respectively for the three operating frequencies. In addition, the reconfigurable Doherty amplifier is successfully linearized when driven with 20 MHz wideband code-division multiple access and 20 MHz long term evolution signals, using a Volterra based digital predistrtion algorithm which exploits a pruned Volterra series. View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras