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Electron Device Letters, IEEE

Issue 4 • Date April 2014

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Displaying Results 1 - 25 of 30
  • Table of contents

    Publication Year: 2014 , Page(s): C1 - C4
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  • IEEE Electron Device Letters publication information

    Publication Year: 2014 , Page(s): C2
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  • Hybrid Amorphous/Nanocrystalline Silicon Schottky Diodes for High Frequency Rectification

    Publication Year: 2014 , Page(s): 425 - 427
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (689 KB) |  | HTML iconHTML  

    We report hybrid amorphous (a-Si)/nanocrystalline (nc-Si) Schottky diodes for rectification at high frequencies. All fabrication steps are done at , making them compatible with processing on plastic. The diodes have a high current density (5 A/cm2 at 1 V and 100 A/cm2 at 2 V) and on-to-off current ratio (over 1000 for bias voltages of 1/-8 V). A 0.01- mm2 hybrid diode has a series resistance of 200 Ω and a capacitance of 7 pF, leading to a cutoff frequency of 110 MHz. As a half-wave rectifier driving a parallel 1- MΩ resistive and 100-nF capacitive load, the dc rectified voltage drops at frequencies , with a -3 dB point at 70 MHz. View full abstract»

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  • Lateral p-n-p Transistors and Complementary SiC Bipolar Technology

    Publication Year: 2014 , Page(s): 428 - 430
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (593 KB) |  | HTML iconHTML  

    Lateral p-n-p transistors and a complementary bipolar technology have been demonstrated for analog integrated circuits. Besides vertical n-p-n's, this technology provides lateral p-n-p's at the cost of one additional lithographic and dry etching step. Both devices share the same epitaxial layers and feature topside contacts to all terminals. The influence on p-n-p current gain of contact topology (circular versus rectangular), effective base width, base/emitter doping ratio, and temperature was studied in detail. In the range -40°C to 300 °C, the current gain of the p-n-p transistor shows a maximum of ~ 37 around 0 °C and decreases to ~ 8 at 300 °C, whereas in the same range, the gain of n-p-n transistors exhibits a negative temperature coefficient. View full abstract»

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  • Impact of Stress Mode on Stochastic BTI in Scaled MG/HK CMOS Devices

    Publication Year: 2014 , Page(s): 431 - 433
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1044 KB) |  | HTML iconHTML  

    Stochastic bias temperature instability (BTI) modeling has gained importance for scaled metal gate/high- k CMOS devices to ensure SRAM circuit functionality. In this letter, we discuss the impact of the BTI stress mode on the ΔVT distribution and the time evolution of VT in small and large area CMOS devices. It is shown that the stress mode has strong impact on the evolution of the threshold voltage distribution in small area devices leading to an increase in the σ-value for constant overdrive stress, whereas no change is observed for constant voltage stress. Since CMOS circuits share the supply voltage, the constant voltage stress σ-values are relevant and thus, the reliability guidance for future CMOS design should be based on constant voltage stress. View full abstract»

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  • Miniaturized 40–60 GHz On-Chip Balun With Capacitive Loading Compensation

    Publication Year: 2014 , Page(s): 434 - 436
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (467 KB) |  | HTML iconHTML  

    A millimeter-wave balun by using the broadside-coupled transmission lines and capacitive loading compensation is proposed and investigated. The balun is designed and verified by using a commercial SiGe BiCMOS technology. The measured results show that in the frequency range of 40-60 GHz, the amplitude mismatching and absolute phase error are less than 0.2 dB and 2.7°, respectively. The compact size of the balun is only 200 μm × 180 μm including grounding shield. View full abstract»

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  • ESD Protection Device With Dual-Polarity Conduction and High Blocking Voltage Realized in CMOS Process

    Publication Year: 2014 , Page(s): 437 - 439
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (438 KB) |  | HTML iconHTML  

    Electrostatic discharge (ESD) protection devices fabricated in a low-voltage CMOS process for communication interface applications typically provide relatively small blocking voltage, thus limiting the interface operating voltage range for which the ESD device can be used. This letter introduces a CMOS-based silicon controlled rectifier with a large blocking voltage beyond ±20 V and a high trigger current. Such a high blocking voltage is achieved by selectively defining native-buffer regions in critical blocking junctions of the device. Experimental characterization of the ESD robustness and standing operation are presented to validate the new device for low capacitance, high-voltage-tolerant communication interface ESD protection applications. View full abstract»

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  • A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs

    Publication Year: 2014 , Page(s): 440 - 442
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (579 KB) |  | HTML iconHTML  

    We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of low-power O2 plasma oxidation, followed by diluted H2SO4 rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is ~0.9 nm/cycle. We illustrate the new process by fabricating Lg=60-nm self-aligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO2 for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/μm(Vds=0.5 V), subthreshold swing of 89 mV/decade, and 102 mV/decade at Vds=0.05 and 0.5 V, respectively, and on current of 326 μA/μm at IOFF=100 nA/μm and Vdd=0.5 V. View full abstract»

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  • Influence of Buffer Carbon Doping on Pulse and AC Behavior of Insulated-Gate Field-Plated Power AlGaN/GaN HEMTs

    Publication Year: 2014 , Page(s): 443 - 445
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1430 KB) |  | HTML iconHTML  

    Pulse behavior of insulated-gate double-field-plate power AlGaN/GaN HEMTs with C-doped buffers showing small current-collapse effects and dynamic RDS,on increase can accurately be reproduced by numerical device simulations that assume the CN-CGa autocompensation model as carbon doping mechanism. Current-collapse effects much larger than experimentally observed are instead predicted by simulations if C doping is accounted by dominant acceptor states. This suggests that buffer growth conditions favoring CN-CGa autocompensation can allow for the fabrication of power AlGaN/GaN HEMTs with reduced current-collapse effects. The drain-source capacitance of these devices is found to be a sensitive function of the C doping model, suggesting that its monitoring can be adopted as a fast technique to assess buffer compensation properties. View full abstract»

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  • 600 V-18 A GaN Power MOS-HEMTs on 150 mm Si Substrates With Au-Free Electrodes

    Publication Year: 2014 , Page(s): 446 - 448
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (713 KB) |  | HTML iconHTML  

    We present the development of an Au-free ohmic contact metallization for high voltage GaN-based high electron mobility transistors (HEMTs). In this letter, low contact resistance (0.81 Ω·mm) is obtained for Au-free electrodes on AlGaN/GaN HEMT structures. Using Au-free ohmic processes, large scale high power GaN metal-oxide-semiconductor HEMTs were successfully fabricated in a procedure fully compatible with standard Si CMOS manufacturing with the maximum drain current of more than 18 A and low OFF-state leakage current of 3×10-7 A at VDS of 600 V. The practicality of the devices was further demonstrated by measurements of the current collapse effects under severe operating conditions and the temperature dependence of the electrical characteristics. View full abstract»

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  • Low RC-Constant Perforated-Channel HFET

    Publication Year: 2014 , Page(s): 449 - 451
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    The novel HFET design using perforated channel region under the gate reduces drain and source parasitic resistances due to the current spreading effect in the source-gate and gate-drain regions. Demonstrated results for AlGaN/GaN HFET show that the RONCG time constant reduces around two times using simple and robust perforated channel device processing. These results are especially important for new generations of power switching transistors. View full abstract»

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  • High-Performance Multilevel Resistive Switching Gadolinium Oxide Memristors With Hydrogen Plasma Immersion Ion Implantation Treatment

    Publication Year: 2014 , Page(s): 452 - 454
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1167 KB) |  | HTML iconHTML  

    Multilevel resistive switching (RS) of gadolinium oxide (GdxOy) memristors treated by hydrogen plasma immersion ion implantation (PIII) was investigated. Hydrogen ions were implanted at the Pt/GdxOy interface to modify the oxygen-vacancy distribution, which was examined by the X-ray photoelectron spectroscopy. After the hydrogen PIII treatment, a forming process is needed to operate the GdxOy memristors and the RS mechanism is changed from Schottky emission to space-charge-limited conduction. Superior multilevel RS properties such as data retention for more than 104 s at 85°C, and sequentially cycling test for more than 103 times with a resistance ratio of approximately one order of magnitude between each state are realized, making the future high-density flash memory possible. View full abstract»

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  • Effect of Nitrous Oxide High Pressure Annealing on the Performance of Low Temperature, Soluble-Based IZO Transistors

    Publication Year: 2014 , Page(s): 455 - 457
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (506 KB) |  | HTML iconHTML  

    The effects of oxygen (O2) and nitrous oxygen (N2O) high pressure annealing (HPA) on soluble indium-zinc oxide (IZO) thin-film transistors (TFTs) were compared. The N2O HPA treatment produced superior device performance compared with the O2 HPA treatment. The N2O HPA-treated device exhibited a reasonable μSAT, low SS, Vth, and high ION/OFF ratio of 1.0 cm2/Vs, 0.09 V/decade, 1.4 V, and 2.3×107, respectively, even at a temperature as low as 200 °C. This improvement was attributed to the supply of reactive oxygen atoms from N2O molecules, leading to the reduction of oxygen vacancies, and a decrease in the impurity concentration of the resulting soluble IZO film. View full abstract»

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  • Effect of Temperature and Electric Field on Degradation in Amorphous InGaZnO TFTs Under Positive Gate and Drain Bias Stress

    Publication Year: 2014 , Page(s): 458 - 460
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (681 KB) |  | HTML iconHTML  

    The mechanism of the electrical degradation in amorphous InGaZnO thin-film transistors under a positive gate and drain bias stress is investigated. The stress tests under various combinations of bias and temperature reveal that the negative shift of transfer curves accompanied by a hump is attributed to not an electric field or heating alone, but the simultaneous effect of them. Furthermore, the mitigated degradation under a pulsed stress of a reduced pulse period from 2 s to 0.1 ms and the difference in output characteristics between a dc sweep and a pulsed sweep measurements imply that self-heating with the high field could be the main cause of the degradation rather than hot-carrier effect. View full abstract»

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  • High-Speed Dual-Gate a-IGZO TFT-Based Circuits With Top-Gate Offset Structure

    Publication Year: 2014 , Page(s): 461 - 463
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (620 KB) |  | HTML iconHTML  

    Owing to bulk-accumulation, dual-gate (DG) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with top- and bottom-gates electrically tied together (DG-driving) exhibit 2.53 times higher ON-current and subthreshold voltage swing of ~ 180 mV/decade, which is 50% lower than that of single-gate (SG)-driven a-IGZO TFTs. Here, through simulation and experimental results, we demonstrate that the use of DG-driven back-channel-etched a-IGZO TFTs with a top-gate offset structure enhances the switching speed of a-IGZO TFT-based circuits. In particular, fabricated SG-driven and DG-driven 11-stage ring oscillators exhibited respective oscillating frequencies of 334 and 781 kHz. View full abstract»

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  • Strong Enhancement in Light Output of GaN-Based LEDs With Graded-Refractive-Index ITO Deposited on Textured V-Shaped Pits

    Publication Year: 2014 , Page(s): 464 - 466
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (382 KB) |  | HTML iconHTML  

    An interesting structure of GaN-based light-emitting diodes (LEDs) with different indium-tin-oxide (ITO) films deposited on naturally textured V-shaped pits (V-pits) is fabricated and studied. The sputtered ITO assists the textured surface to get a better contact and thus reduces the forward voltage. Moreover, the ITO films prepared by different methods can serve as graded-refractive-index antireflective coatings, which can enhance the performance of the V-pits LED further. The results show that the V-pits LED with two layers ITO films have a stronger light output power than the reference LED by 52.1% at 20 mA, and the forward voltage is only a little higher than the standard LED. View full abstract»

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  • Improved Performance of 365-nm LEDs by Inserting an Un-Doped Electron-Blocking Layer

    Publication Year: 2014 , Page(s): 467 - 469
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB) |  | HTML iconHTML  

    In this letter, the ultraviolet light emitting diode (UV-LED) with an undoped Al0.23Ga0.77N electron-blocking layer (EBL) between the p-type doped Al0.23Ga0.77N EBL and last barrier was proposed. After inserting the undoped EBL, both the photoluminescence and electroluminescence (EL) characteristics of UV-LED were significantly improved. As the undoped EBL was inserted, the 365-nm UV-LED possessed 400% improvement in output power (at 19 A/cm2). However, the enhancement in output power was significantly reduced to 20% when the insertion of undoped EBL was applied for 375-nm UV-LED. In addition, the long-term reliability was enhanced efficiently with the addition of undoped EBL. After the aging test for 1032 h, it presented the 365-nm UV-LED inserted with an undoped EBL had the obvious improvements both in the characteristics of EL intensity and leakage current density. View full abstract»

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  • Micromachined Air-Lifted Pillar Arrays for Terahertz Devices

    Publication Year: 2014 , Page(s): 470 - 472
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (505 KB) |  | HTML iconHTML  

    Micromachined air-lifted pillar arrays have been designed, fabricated, and characterized in the range of 1-3 THz. The pillar arrays consist of high-aspect-ratio epoxy structures defined by ultraviolet lithography followed by sputtered metallization. A Bruker 113v Fourier transform infrared spectrometer (FTIR) system has been used to characterize the fabricated air-lifted pillar arrays for both p-( E-field parallel to the plane of incidence) and s-( E-field perpendicular to the plane of incidence) polarized incident waves. Measurement results are verified using resonant frequency calculation and Floquet mode simulation. In the p -polarization measurement, the pillar arrays with a diameter of 5 μm, and heights of 28, 39, 54, and 60 μm show quarter wavelength resonant frequencies at 2.16, 1.81, 1.46, and 1.38 THz, respectively, as predicted. Since the air dielectric architecture has no dielectric loss, it would enable highly power efficient terahertz devices such as a monopole antenna, a frequency selective surface, and an electromagnetic absorber. View full abstract»

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  • Band-to-Band Tunneling in Ge-Rich SiGe Devices

    Publication Year: 2014 , Page(s): 473 - 475
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    Germanium is one of the promising materials for future CMOS technologies, due to its high carrier mobility and low Schottky barrier height (for PMOS). However, the presence of a small direct gap (in addition to the main indirect gap at the L-point) can result in significant band-to-band tunneling (BTBT), even at low voltages. If not remedied, it is easily the dominant BTBT mechanism. In this letter, the dependence of BTBT on the alloy composition in Ge-rich SiGe is studied using detailed simulation of the bandstructure. It is shown that even a very low stoichiometric fraction of Si in a FinFET results in a dramatic reduction of direct BTBT, much more so than in a corresponding p-i-n diode. View full abstract»

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  • High Heat Flux, High Temperature Cooling of Electronics With Thermoelectric Devices

    Publication Year: 2014 , Page(s): 476 - 478
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    Single couple PbTe/TAGS-85 and thin-film superlattice Bi2Te3-based thermoelectric couples operated in a downhill active cooling mode, where the cold side temperature (Tc) is above that of the heat sink (Th), are shown to be able to pump heat loads of 204 W/cm2 (Tc ~ 300°C) and 329 W/cm2 (Tc ~ 150°C), respectively, using a 25 °C heat sink temperature. Such TE devices would be useful in active cooling of wide bandgap RF electronics operating ~ 300°C and ~ 150°C, respectively. View full abstract»

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  • New Weighted Time Lag Method for the Analysis of Random Telegraph Signals

    Publication Year: 2014 , Page(s): 479 - 481
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1140 KB) |  | HTML iconHTML  

    A new method for the characterization of random telegraph signals (RTSs) is presented. The method, which is based on the time lag plot, is illustrated using Monte Carlo generated RTS traces and applied to identify the contribution of defects in multilevel RTS measured in a pMOS transistor. The results show that the new method provides a powerful and easily implementable technique to obtain the parameters of the defects responsible of multilevel RTS, even when the background noise is relevant. View full abstract»

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  • Low-Cost pH Sensors Based on Low-Voltage Oxide-Based Electric-Double-Layer Thin Film Transistors

    Publication Year: 2014 , Page(s): 482 - 484
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (885 KB) |  | HTML iconHTML  

    Indium-tin-oxide-based electric-double-layer (EDL) thin-film transistors (TFTs) are used as pH sensors. Such EDL devices show a low operation voltage of ~ 1.5 V and a high field-effect electron mobility (μFE) of ~ 20 cm2·V-1·s-1 when phosphorous-doped nanogranular SiO2-based electrolyte films are used as the gate dielectric. The pH sensor based on such EDL TFT exhibits a high sensitivity of 58.1 mV·pH-1 and a good linearity in the pH range from 2 to 12. In addition, such pH sensors present a low threshold voltage drift rate of 2.2 mV·h-1 and a hysteresis voltage of 8.3 mV after a pH loop of 7→ 4→ 7→ 10→7. View full abstract»

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  • Segmented Electrodes for Piezoelectric Energy Harvesters

    Publication Year: 2014 , Page(s): 485 - 487
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1702 KB) |  | HTML iconHTML  

    This letter studies the impact of electrode segmentation on energy harvesting with piezoelectrics. For cases where the load can be distributed, it is concluded that segmentation of electrodes helps to improve energy content by minimizing surface currents. Using a ribbon of polyvinylidene fluoride under tension as an example, we show that using a six segmented electrode improves energy content by a factor of 2.5. Power delivery remains almost constant except for an anomalous increase when the number of segments is made large. Models are developed to predict improvements in energy content and power delivery. View full abstract»

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  • SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture

    Publication Year: 2014 , Page(s): 488 - 490
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1392 KB) |  | HTML iconHTML  

    A novel nonvolatile flip-flop (NVFF) using a magnetic tunnel junction (MTJ) is presented for power gating architecture. The proposed NVFF exploits spin Hall effect (SHE) for fast and low-power data backup into MTJs before the power is gated off. Owing to the high spin injection efficiency of SHE, the estimated write current for backup operation is lower than 40 μA. Due to the low write current requirement, we do not introduce a dedicated write driver circuit. Instead, we utilize the cross-coupled inverters in the slave latch to perform the backup operation, resulting in low area overhead. The simulation results show 10× improvement in backup energy when compared with previous works on spin transfer torque-based NVFFs. View full abstract»

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  • A Low-Loss Directly Heated Two-Port RF Phase Change Switch

    Publication Year: 2014 , Page(s): 491 - 493
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (831 KB) |  | HTML iconHTML  

    In this letter, we report on the design, fabrication, and measured results of a directly heated phase change RF switch (or via) using germanium telluride in a four-terminal configuration. The switch is heated using a separate heater path combining the advantages of directly heated vias, such as low power dissipation for phase transition, and indirectly heated vias, such as high power handling capability. The phase change switch shows an insertion loss of less than 0.6 dB and an isolation of higher than 20 dB at frequencies up to 20 GHz, indicating a cutoff frequency of more than 3.7 THz. The switch area is only 4 μm× 6 μm, which is smaller than RF MEMS switches with similar insertion loss performance. To the best of our knowledge, this is the first report on a four-terminal, directly heated, RF phase change switch. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Amitava Chatterjee