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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 1 • Date Jan 1994

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Displaying Results 1 - 12 of 12
  • FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

    Publication Year: 1994 , Page(s): 1 - 12
    Cited by:  Papers (172)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1020 KB)  

    The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height K-feasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUT's by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUT's by up to 50% compared to the three previous methods View full abstract»

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  • QFP wiring problem-introduction and analytical considerations

    Publication Year: 1994 , Page(s): 48 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (820 KB)  

    A novel Josephson device with many desirable properties-fast switching speed, high operation frequency, and low power dissipation-has been researched these several years: the Quantum Flux Parametron (QFP). This paper discusses the interconnection problem of QFP circuits, where wire inductance matching and high clock rate restrict the lengths of interconnection wires. A layout model of QFP interconnection wires is clarified, and the effects of wire inductance matching on interconnection area and wire length are analyzed. The limitation comes from the bound of the number of squares of wires, therefore similar effects will exist where wire resistance is bounded. This paper discusses a simple wiring and buffering algorithm for QFP circuits, in which wire inductance is adjusted and the maximum wire length is controlled, to prove that any logic is realizable as a QFP circuit View full abstract»

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  • A multi-probe approach for MCM substrate testing

    Publication Year: 1994 , Page(s): 110 - 121
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB)  

    Multi-chip module (MCM) technology has become an important means to package high performance systems. An important task during the packaging process is to check for possible open, short, and high resistance faults in the wiring networks of the bare MCM substrates, which is called substrate testing. After examining several substrate testing methodologies, we find that multi-probe or k-probe testers are cost-effective for substrate testing. However, the testing speed of this method is not high; hence, we focus on improving the throughput by reducing the number of tests and by deriving good probe routes. For test size reduction, we propose a routing tree model to capture the wiring structure of a given net; then by taking advantage of the routing tree, we generate a minimum number of tests while ensuring complete open fault coverage. Our algorithm reduces the number of tests by up to 50% compared to that of previous approaches. Given a routing tree with its node degree bounded by a constant, our test generation algorithm runs in linear time with respect to the number of leaves of the tree. For probe route scheduling, we observe that in order to obtain a balanced and efficient scheduling, the routes of different probes must be considered simultaneously, which motivates our Multi-Dimensional Traveling Salesman Problem (MDTSP) formulation. Our package has been installed on existing substrate testers and has achieved encouraging results View full abstract»

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  • Algorithms for the transient simulation of lossy interconnect

    Publication Year: 1994 , Page(s): 96 - 104
    Cited by:  Papers (21)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    In this paper, a new linear-time technique is described for the simulation of lossy lines with frequency-independent R, L, C and G. Exact analytic forms are shown to exist for the frequency-independent lossy line, with application in both the new technique and the conventional convolution method. Numerical convolution formulae that exploit the analytic forms are presented. Experimental results for industrial circuits indicate that the new technique can be 10 and 50 times faster than the convolution and lumped-RLC methods, respectively, for long simulations View full abstract»

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  • Single-layer global routing

    Publication Year: 1994 , Page(s): 38 - 47
    Cited by:  Papers (13)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB)  

    We introduce the single-layer global routing problem (SLGRP), also called homotopic routing or rubber-band-equivalent routing, and propose a technique for solving it. Given a set of nets, the proposed technique first determines the routing sequence based on the estimated congestion, the bounding-box length and priority. Then, it finds a routing path, being a sequence of tiles, for each net (one net at a time), avoiding “congested” areas. The overall goal of the algorithm is to maximize the number of routed nets. The proposed global router is the first true single-layer global router ever reported in the literature. The size of tiles, w×w, is an input parameter in our algorithm. For w=1, the proposed global router serves as an effective detailed router. An optimal postprocessing algorithm, minimizing wire length and number of bends, under homotopic transformation, is presented. The technique has been implemented and tried out for randomly generated data. The algorithm is very efficient and produces good results View full abstract»

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  • On the intrinsic Rent parameter and spectra-based partitioning methodologies

    Publication Year: 1994 , Page(s): 27 - 37
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1172 KB)  

    The complexity of circuit designs has necessitated a top-down approach to layout synthesis. A large body of work shows that a good layout hierarchy, or partitioning tree, as measured by the associated Rent parameter, will correspond to an area-efficient layout. We define the intrinsic Rent parameter of a netlist to be the minimum possible Rent parameter of any partitioning tree for the netlist. Experimental results show that spectra-based ratio cut partitioning algorithms yield partitioning trees with the lowest observed Rent parameter over all benchmarks and over all algorithms tested. For examples where the intrinsic Rent parameter is known, spectral ratio cut partitioning yields a partitioning tree with Rent parameter essentially identical to this theoretical optimum. These results have deep implications with respect to both the choice of partitioning algorithms for top-down layout, as well as new approaches to layout area estimation. The paper concludes with directions for future research, including several promising techniques for fast estimation of the (intrinsic) Rent parameter View full abstract»

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  • Semiconductor wafer representation for TCAD

    Publication Year: 1994 , Page(s): 82 - 95
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1392 KB)  

    This paper describes the Semiconductor Wafer Representation (SWR) for representing and manipulating wafer state during process and device simulation. The goal of the SWR is to provide an object-oriented interface to a collection of functions designed for developing and integrating Technology CAD (TCAD) applications. By providing functions which can be common across many applications, we aim to greatly reduce tool development and integration time. Corporate, vendor, and university TCAD developers have worked together under the auspices of the CAD Framework Initiative to create an architecture and C++ programming interface for an SWR 1.0 draft standard. Here we describe this architecture and the results of creating and using a prototype implementation of the standard both to integrate existing TCAD tools and to develop simple new tools View full abstract»

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  • JFET circuit simulation using SPICE implemented with an improved model

    Publication Year: 1994 , Page(s): 105 - 109
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    Junction field-effect transistor (JFET) circuit simulation using an existing physics-based JFET model is presented. This improved model has more predictive capability than the conventional JFET model employed in SPICE. Furthermore, it treats the linear and saturation regions in a unified manner and includes the subthreshold behavior, an effect not accounted for in the conventional model. The improved model is implemented into PSPICE run on a Sun workstation, and steady-state and transient responses are simulated for a JFET switching circuit and a JFET voltage follower circuit. Results obtained from the improved model compare favorably with that obtained from a two-dimensional device simulator PISCES and from measurements. For JFETs operating outside the subthreshold region, the conventional model with optimized parameters (extracted from measurements) also shows good accuracy. However, large discrepancies arise from the conventional model if JFETs are biased in the subthreshold region or if default model parameters are used View full abstract»

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  • Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs

    Publication Year: 1994 , Page(s): 122 - 134
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1332 KB)  

    We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. We present a technique which allows for the verification of a specific class of systems, namely systems with synchronous globally timed control. To a first approximation, these are systems where a single controller directs the data through the data path and decides (globally) when to move the data. We address the verification of these systems against a Signal Flow Graph (SFG) specification, or a specification in an applicative language such as SILAGE. In this paper, a method is presented for verifying the implementation against an intermediate SFG, which is an expansion of the original specification in such a way that all the operations correspond to Register Transfers (RT's) in the implementation. In this SFG, complex arithmetic operations such as multiplications may have been decomposed into simpler ones, such as shifts and additions, and new operations may have been introduced for maintaining iteration indices and computing addresses of memory locations. SFG's can be viewed as maximally parallel synchronous machines. Both the implementation and the specification are then Finite State Machines, having string functions (input/output mappings) associated with them. Correctness is taken to mean that a certain relation (the β-relation) holds between these string functions View full abstract»

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  • Routability-driven technology mapping for lookup table-based FPGA's

    Publication Year: 1994 , Page(s): 13 - 26
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1376 KB)  

    A new algorithm for technology mapping of lookup table-based Field-Programmable Gate Arrays (FPGA's) is presented. It has the capability of producing compact designs (minimizing the number of cells (CLB's)), as well as the flexibility of trading routability with compactness of a design. Research in this area has focussed on minimizing the number of cells. However, minimizing the number of cells without regard to routability is ineffective. Since placement and routing is really the most time-consuming part of the FPGA design process, producing a routable design with a slightly larger number of cells is preferable than producing a design using fewer cells which is difficult to route, or in the worst case unroutable. We have implemented our algorithm in the Rmap program, and studied routability of two other mappers with respect to Rmap. Rmap produces mappings with better routability characteristics, and more significantly Rmap produces routable mappings when other mappers do not View full abstract»

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  • Circuit analysis and optimization driven by worst-case distances

    Publication Year: 1994 , Page(s): 57 - 71
    Cited by:  Papers (64)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1432 KB)  

    In this paper, a new methodology for integrated circuit design considering the inevitable manufacturing and operating tolerances is presented. It is based on a new concept for specification analysis that provides exact worst-case transistor model parameters and exact worst-case operating conditions. Corresponding worst-case distances provide a key measure for the performance, the yield, and the robustness of a circuit. A new deterministic method for parametric circuit design that is based on worst-case distances is presented. It comprises nominal design, worst-case analysis, yield optimization, and design centering. In contrast to current approaches, it uses standard circuit simulators and at the same time considers deterministic design parameters of integrated circuits at reasonable computational costs. The most serious disadvantage of geometric approaches to design centering is eliminated, as the method's complexity increases only linearly with the number of design variables View full abstract»

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  • VISTA-the data level

    Publication Year: 1994 , Page(s): 72 - 81
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB)  

    In order to meet the requirements of advanced process and device design, a new generation of technology CAD (TCAD) simulation frameworks is emerging. These are based on a data level providing a common data interchange format. Such a format must be suitable for building simulation databases, and needs to be supported by tools and a procedural interface with multi-language bindings for data storage and retrieval by application programs. In this work, the data level of the Viennese integrated system for TCAD applications (VISTA), which includes the profile interchange format (PIF), the PIF binary file manager (PBFM) and the PIF application interface (PAI), is described from a framework point of view View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu