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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 4 • Date April 2014

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2014, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2014, Page(s): C2
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  • Guest Editorial: Special Section on Contemporary and Emerging Issues in Physical Design

    Publication Year: 2014, Page(s):493 - 494
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  • Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure

    Publication Year: 2014, Page(s):495 - 506
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1143 KB) | HTML iconHTML

    In this paper, we demonstrate that standard cell design methodology can be applied to design vertical slit field effect transistor (VeSFET)-based ASICs with modern CMOS EDA tools. We study a family of VeSFET canvases-chain canvases that improve performance and power consumption of circuits mapped to them compared to circuits implemented with VeSFET canvases composed of isolated transistors. We com... View full abstract»

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  • Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment

    Publication Year: 2014, Page(s):507 - 518
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1262 KB) | HTML iconHTML

    Retention registers have been widely used in power gated designs to store data during sleep mode. However, their excessive area and leakage power render it imperative to minimize the total retention storage size. The current industry practice replaces all registers with singlebit retention ones, which significantly limits the design freedom and yields suboptimal designs. Toward this, for the first... View full abstract»

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  • On the Deployment of On-Chip Noise Sensors

    Publication Year: 2014, Page(s):519 - 531
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB) | HTML iconHTML

    Runtime noise management systems can enforce power integrity without significantly increasing design margins. These systems typically respond to on-chip noise sensors to accurately capture voltage emergencies. Unfortunately, it remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection, or how to best set the threshold volt... View full abstract»

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  • Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem

    Publication Year: 2014, Page(s):532 - 545
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (846 KB) | HTML iconHTML

    In this paper, we present and analyze four efficient models that produce significantly improved results by optimizing conflicting power and skew objectives in the clock network buffer sizing problem. Each model is in geometric programming format and has certain advantages, such as maximum reduction in power, robustness to process variation, and striking a balance between skew and power optimizatio... View full abstract»

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  • Effective Method for Simultaneous Gate Sizing and V th Assignment Using Lagrangian Relaxation

    Publication Year: 2014, Page(s):546 - 557
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (769 KB) | HTML iconHTML

    This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces ... View full abstract»

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  • PushPull: Short-Path Padding for Timing Error Resilient Circuits

    Publication Year: 2014, Page(s):558 - 570
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1429 KB) | HTML iconHTML

    Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short-path padding (hold time fixing) problem in resilient circuits is far severer than conventi... View full abstract»

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  • Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs

    Publication Year: 2014, Page(s):571 - 584
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1805 KB) | HTML iconHTML

    Escape routing has become a critical issue in high-speed PCB routing. Most of the previous work paid attention to either differential-pair escape routing or single-signal escape routing, but few considered them together. In this paper, a significant three-stage algorithm is proposed to solve the problem of escape routing of both differential pairs and single signals (mixed-pattern signals). First,... View full abstract»

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  • Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations

    Publication Year: 2014, Page(s):585 - 598
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB) | HTML iconHTML

    The dynamic stability margin of SRAM is largely suppressed at nanoscale due to not only dynamic noise but also process variation. This paper introduces an analog verification for SRAM dynamic stability under threshold-voltage variations. A zonotope-based reachability analysis by the backward Euler method is deployed for SRAM dynamic stability in state space with consideration of SRAM nonlinear dyn... View full abstract»

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  • Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth Operations

    Publication Year: 2014, Page(s):599 - 612
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    The problem of accuracy evaluation is one of the most time consuming tasks during the fixed-point refinement process. Analytical techniques based on perturbation theory have been proposed in order to overcome the need for long fixed-point simulation. However, these techniques are not applicable in the presence of certain operations classified as un-smooth operations. In such circumstances, fixed-p... View full abstract»

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  • Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing

    Publication Year: 2014, Page(s):613 - 626
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1125 KB) | HTML iconHTML

    Traditional solutions to antenna effect, such as jumper insertion and diode insertion performed at post-route stage may produce extra vias and degrade circuit performance. Previous work suggests combining layer assignment, jumper insertion, and diode insertion together to achieve a better design quality with less additional cost. Based on our observations on global and local antenna violations, th... View full abstract»

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  • Error Detection and Recovery for ECC: A New Approach Against Side-Channel Attacks

    Publication Year: 2014, Page(s):627 - 637
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (481 KB) | HTML iconHTML

    Side channel attacks allow an attacker to retrieve secret keys with far less effort than other attacks. Countermeasures against these attacks should be considered during cryptosystem design. This paper presents a novel low-cost error detection and recovery scheme (LOEDAR) to counter fault attacks. The proposed architecture retains the efficiency of the Montgomery ladder algorithm and shows strong ... View full abstract»

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  • Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States

    Publication Year: 2014, Page(s):638 - 642
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (409 KB) | HTML iconHTML

    Test data compression methods reduce the input test data volume by allowing compressed tests to be stored on a tester. Additional reductions in the input test data volume can be achieved if each stored test is used for producing several different tests. Skewed-load tests create a unique opportunity to expand a stored test into several different skewed-load tests by continuing to shift the scan-in ... View full abstract»

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  • Latency Analysis for Sequential Circuits

    Publication Year: 2014, Page(s):643 - 647
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (126 KB) | HTML iconHTML

    Verifying correctness is a major bottleneck in today's circuit and system design. Verification includes the tasks of error detection, error localization, and error correction in an implemented design, as well as the analysis and avoidance of transient faults. For all those tasks, knowing when an assignment to signals becomes observable at the outputs and for how long it influences the system is im... View full abstract»

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  • 2014 IEEE Compound Semiconductor IC Symposium

    Publication Year: 2014, Page(s): 648
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2014, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2014, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu