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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 4 • Date April 2014

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2014 , Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2014 , Page(s): C2
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  • Guest Editorial: Special Section on Contemporary and Emerging Issues in Physical Design

    Publication Year: 2014 , Page(s): 493 - 494
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  • Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure

    Publication Year: 2014 , Page(s): 495 - 506
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    In this paper, we demonstrate that standard cell design methodology can be applied to design vertical slit field effect transistor (VeSFET)-based ASICs with modern CMOS EDA tools. We study a family of VeSFET canvases-chain canvases that improve performance and power consumption of circuits mapped to them compared to circuits implemented with VeSFET canvases composed of isolated transistors. We compare the designs implemented with a commercial low power CMOS library and corresponding VeSFET libraries. VeSFET-based designs demonstrate significant power reduction as compared to the CMOS-based designs at the same performance. View full abstract»

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  • Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment

    Publication Year: 2014 , Page(s): 507 - 518
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    Retention registers have been widely used in power gated designs to store data during sleep mode. However, their excessive area and leakage power render it imperative to minimize the total retention storage size. The current industry practice replaces all registers with singlebit retention ones, which significantly limits the design freedom and yields suboptimal designs. Toward this, for the first time in the literature, we propose the concept and the design of multibit retention registers, with which only selected registers need to be replaced. The technique can significantly reduce the number of bits that need to be stored and thus the leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode by 84% along with additional mode transition latency of 6 to 11 clock cycles, compared with the singlebit retention register-based design. View full abstract»

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  • On the Deployment of On-Chip Noise Sensors

    Publication Year: 2014 , Page(s): 519 - 531
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    Runtime noise management systems can enforce power integrity without significantly increasing design margins. These systems typically respond to on-chip noise sensors to accurately capture voltage emergencies. Unfortunately, it remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection, or how to best set the threshold voltage for these sensors. In this paper, we formally define the problem of noise sensor placement along with a novel sensing quality metric to be maximized. We then put forward an efficient algorithm to solve it, which is proven to attain the best result in the class of polynomial complexity approximations. We further solve the problem to minimize the system failure rate subject to a given runtime performance loss (RPL) constraint. Experimental results on a set of industrial power grid designs show that, compared to a simple average-noise based heuristic and two state-of-the-art temperature sensor placement algorithms aimed at recovering the full map or capturing the hot spots at all times, the proposed method on average can reduce the miss rate of voltage emergency detections by 7.4x, 15x, and 6.2x, respectively. The trade-off between the system failure rate and the RPL is also presented. To the best of the authors' knowledge, this is the very first in-depth work on noise sensor deployment. View full abstract»

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  • Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem

    Publication Year: 2014 , Page(s): 532 - 545
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (846 KB) |  | HTML iconHTML  

    In this paper, we present and analyze four efficient models that produce significantly improved results by optimizing conflicting power and skew objectives in the clock network buffer sizing problem. Each model is in geometric programming format and has certain advantages, such as maximum reduction in power, robustness to process variation, and striking a balance between skew and power optimization. The buffer sizing problem is formulated as a geometric programming problem to provide globally optimal solutions to the four models. We also show that a geometric programming multiobjective model can be used to optimize both power and skew without requiring any tuning from a designer. The presented self-tuning multiobjective formulation not only provides optimal solutions for buffer sizes, but also finds the tuning parameters that result in overall combined reduction in power and skew without loss of convexity. The effectiveness of the models are illustrated on several publicly available benchmarks. The models provide on average 40% to 60% improvement in power while reducing skew in several cases. We have also proposed a smart heuristic for discretization of the continuous geometric programming solution that preserves skew and power. Finally, we provide a guideline for designers to decide which one of the proposed models is the most appropriate for their needs. View full abstract»

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  • Effective Method for Simultaneous Gate Sizing and V th Assignment Using Lagrangian Relaxation

    Publication Year: 2014 , Page(s): 546 - 557
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (769 KB) |  | HTML iconHTML  

    This paper presents a fast and effective approach to gate-version selection and threshold voltage, Vth, assignment. In the proposed flow, first, a solution without slew and load violation is generated. Then, a Lagrangian Relaxation (LR) method is used to reduce leakage power and achieve timing closure while keeping the circuit no or few violations. If the set of gate-versions given by LR produces a circuit with negative slack, a timing recovery method is applied to find near zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks, the leakage power of our solutions is, on average, 9.53% smaller than and 12.45% smaller than . The sizing produced using our approach achieved the first place in the ISPD 2013 Discrete Gate Sizing Contest with, on average, 8.78% better power results than the second place tool. With new timing calculation applied, this flow can provide, on average, an extra 9.62% power reduction compared to the best Contest results. This flow is also the first gate sizing method to report violation-free solutions for all benchmarks of the ISPD 2013 Contest. View full abstract»

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  • PushPull: Short-Path Padding for Timing Error Resilient Circuits

    Publication Year: 2014 , Page(s): 558 - 570
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    Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short-path padding (hold time fixing) problem in resilient circuits is far severer than conventional IC design. Therefore, in this paper, we focus on the short-path padding problem to enable the timing error detection and correction mechanism of resilient circuits. Unlike recent prior work adopts greedy heuristics with a local view, we determine the padding values and locations with a global view. Moreover, we utilize spare cells and a dummy metal to further achieve the derived padding values at physical implementation. Experimental results show that our method is promising to validate timing error-resilient circuits. View full abstract»

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  • Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs

    Publication Year: 2014 , Page(s): 571 - 584
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    Escape routing has become a critical issue in high-speed PCB routing. Most of the previous work paid attention to either differential-pair escape routing or single-signal escape routing, but few considered them together. In this paper, a significant three-stage algorithm is proposed to solve the problem of escape routing of both differential pairs and single signals (mixed-pattern signals). First, differential pairs are preconditioned to reduce the complication of the problem. Then, a unified ILP model is used to formulate the problem and a novel Boolean coding-driven algorithm is proposed to avoid mixed crossings. Finally, a slice-based method is presented to prune the variables and speed up the algorithm. Experimental results show that the proposed method is very effective. For single-pattern escape routing, it can solve all the test cases in short time and reduce wire length and chip area by 16.1% and 15.5%, respectively. For mixed-pattern escape routing, it can increase the routability by 17.5% and reduce the wire length by 14.1% compared to a two-stage method. At the same time, the proposed method can effectively avoid mixed crossings with only a little increase on wire length. Furthermore, with slice-based speedup strategy, the method can reduce the solving time by 76.7%. View full abstract»

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  • Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations

    Publication Year: 2014 , Page(s): 585 - 598
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    The dynamic stability margin of SRAM is largely suppressed at nanoscale due to not only dynamic noise but also process variation. This paper introduces an analog verification for SRAM dynamic stability under threshold-voltage variations. A zonotope-based reachability analysis by the backward Euler method is deployed for SRAM dynamic stability in state space with consideration of SRAM nonlinear dynamics. It can simultaneously consider multiple SRAM variation sources without multiple repeated computations. What is more, sensitivity analysis is developed for zonotope to optimize SRAM designs departing from unsafe regions by simultaneously tuning multiple SRAM device parameters. In addition, compared to the SRAM optimization by single-parameter small-signal sensitivity, the proposed method can converge faster with higher accuracy. As shown by numerical experiments, the proposed optimization method can achieve 600× speedup on average when compared to the repeated Monte Carlo simulations under the similar accuracy. View full abstract»

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  • Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth Operations

    Publication Year: 2014 , Page(s): 599 - 612
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    The problem of accuracy evaluation is one of the most time consuming tasks during the fixed-point refinement process. Analytical techniques based on perturbation theory have been proposed in order to overcome the need for long fixed-point simulation. However, these techniques are not applicable in the presence of certain operations classified as un-smooth operations. In such circumstances, fixed-point simulation should be used. In this paper, an algorithm detailing the hybrid technique which makes use of an analytical accuracy evaluation technique used to accelerate fixed-point simulation is presented. This technique is applicable to signal processing systems with both feed-forward and feedback interconnect topology between its operations. The acceleration obtained as a result of applications of the proposed technique is consistent with fixed-point simulation, while reducing the time taken for fixed-point simulation by several orders of magnitude. View full abstract»

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  • Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing

    Publication Year: 2014 , Page(s): 613 - 626
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1125 KB) |  | HTML iconHTML  

    Traditional solutions to antenna effect, such as jumper insertion and diode insertion performed at post-route stage may produce extra vias and degrade circuit performance. Previous work suggests combining layer assignment, jumper insertion, and diode insertion together to achieve a better design quality with less additional cost. Based on our observations on global and local antenna violations, this paper proposes an antenna-safe single-net layer assignment (AS-SLA), which first enumerates all antenna-safe layer assignment solutions of a net, and then extracts the minimum-cost one for the net. AS-SLA can minimize via count and separators as well. In addition, an antenna avoidance layer assignment flow (AALA) adopting AS-SLA as its kernel not only avoids global antenna violations, but also eliminates local antenna violations. Experimental results reveal that, in 16 benchmarks, AALA can yield ten antenna-violation-free assignments, while the algorithms of other works yield no antenna-violation-free assignment. However, AALA performs about seven times slower than other antenna-aware layer assignment algorithm. Accordingly, two acceleration techniques are proposed to reduce the runtime of AALA by 57.6%. View full abstract»

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  • Error Detection and Recovery for ECC: A New Approach Against Side-Channel Attacks

    Publication Year: 2014 , Page(s): 627 - 637
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    Side channel attacks allow an attacker to retrieve secret keys with far less effort than other attacks. Countermeasures against these attacks should be considered during cryptosystem design. This paper presents a novel low-cost error detection and recovery scheme (LOEDAR) to counter fault attacks. The proposed architecture retains the efficiency of the Montgomery ladder algorithm and shows strong resistance to both environmental-induced faults as well as attacker-introduced faults. Moreover, the proposed LOEDAR scheme is compatible with most existing countermeasures against various power analysis attacks including differential power analysis and its variants, which makes it extendable to a comprehensive countermeasure against both fault attacks and power analysis attacks. View full abstract»

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  • Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States

    Publication Year: 2014 , Page(s): 638 - 642
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    Test data compression methods reduce the input test data volume by allowing compressed tests to be stored on a tester. Additional reductions in the input test data volume can be achieved if each stored test is used for producing several different tests. Skewed-load tests create a unique opportunity to expand a stored test into several different skewed-load tests by continuing to shift the scan-in state for one or more additional clock cycles. This opportunity for test data volume reduction beyond test data compression is introduced in this paper. The paper describes a procedure that starts from a given skewed-load test set. The procedure removes tests from the test set and recovers the fault coverage by applying several tests based on every stored test. View full abstract»

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  • Latency Analysis for Sequential Circuits

    Publication Year: 2014 , Page(s): 643 - 647
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (126 KB) |  | HTML iconHTML  

    Verifying correctness is a major bottleneck in today's circuit and system design. Verification includes the tasks of error detection, error localization, and error correction in an implemented design, as well as the analysis and avoidance of transient faults. For all those tasks, knowing when an assignment to signals becomes observable at the outputs and for how long it influences the system is important. In this letter, we propose a minimal and maximal latency measure for sequential circuits. This measure explains how long a circuit's state and outputs depend on input stimuli. Exact and heuristic algorithms are discussed to determine the measure. We evaluate the algorithms on state-of-the-art designs. Experimental results show how the measure provides insight into the behavior of circuit designs. View full abstract»

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  • 2014 IEEE Compound Semiconductor IC Symposium

    Publication Year: 2014 , Page(s): 648
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2014 , Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2014 , Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu