By Topic

Components, Hybrids, and Manufacturing Technology, IEEE Transactions on

Issue 8 • Date Dec 1993

Filter Results

Displaying Results 1 - 25 of 34
  • Investigation of plasma effects on plastic packages delamination and cracking

    Publication Year: 1993 , Page(s): 919 - 924
    Cited by:  Papers (7)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    The use of a nonreactive plasma formed in a radio frequency discharge as a treatment to various substrates to reduce or eliminate the organic and inorganic contamination, thereby preventing intimate interfacial contact, was investigated. Argon was investigated as the plasma gas. The effects of time chamber pressure, and power were studied. A goniometer was utilized to measure wetting contact angles as a quantitative measure of the cleaning effectiveness of the surface treatment. Electron spectroscopy for chemical analysis (ESCA) data are correlated with substrate hydrophilicity, delamination, and package cracking. The results show the argon plasma treatment to be an effective means of reducing interfacial organic and inorganic contamination and improving the polyimide-to-mold-compound. The improvement in package cracking performance brought about by the argon plasma treatment is significant View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluation of tumbling processes of multilayer ceramic capacitors for surface mount device applications

    Publication Year: 1993 , Page(s): 822 - 827
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    During a tumbling process, sharp corners of multilayer ceramic chip capacitors are rounded to obtain smooth corners. The sharp corners of chip capacitors are susceptible to breakage during pick and place machine operation used in surface mount technologies. Tumbling of chip capacitors minimizes such breakage. The author describes various tumbling processes and their effect on electrical properties and life test performance of 0.1 μF lead based multilayer capacitors, in 0905, 1005, and 1206 sizes. In conclusion, this study recommends a tumbling process involving bisque fired capacitors over other processes for lead based multilayer capacitors. A short discussion on the general methodology of the tumbling process is included View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Directly deposited fluxless lead-indium-gold composite solder

    Publication Year: 1993 , Page(s): 789 - 793
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    Lead-indium-gold multilayer composite solder has been developed for bonding electronic devices without the use of flux. The composite is deposited directly on GaAs wafers in high vacuum to inhibit indium oxidation. The gold layer on the composite further protects the indium layer from oxidation in atmosphere. Using the composite solder without flux, GaAs dies have been successfully bonded to alumina substrates at a process temperature of 250°C. Nearly perfect joints are achieved as verified by a scanning acoustic microscope (SAM). Scanning electron microscopy (SEM) and energy-dispersive X-ray (EDX) spectroscopy results indicate that the joint consists of AuIn2 grains embedded in an In-Pb solid solution phase, as predicted from the Au-In-Pb phase diagram. Thermal shock as well as shear tests confirm that high quality bonding is obtained with the lead-indium-gold composite View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Resistive signal line wiring net designs in multichip modules

    Publication Year: 1993 , Page(s): 909 - 918
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (756 KB)  

    To approximate the frequency dependence of the characteristic impedance and signal attenuation of a DC resistive transmission line, formulas with one pole and one zero on the negative real axis are proposed. The algebraic time-domain solutions for the near-end and far-end voltages of this line, which is driven by a constant resistance source, are derived. The far end of this line is either open-circuited or terminated by a constant resistance load. Nomographs to guide the multichip module (MCM) wiring net designs are developed and presented. Their application is illustrated by an MCM-D address bus wiring net design example View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Encapsulant for fatigue life enhancement of controlled-collapse chip connection (C4)

    Publication Year: 1993 , Page(s): 863 - 867
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    The characterization of a liquid silica-filled system for maximum processability of controlled-collapse chip connection (C4), or flip-chip connection, chips is described. Critical thermomechanical properties were studied to ensure that both ceramic module and card assembly conditions can be sustained. Both rheological properties and cure kinetics were optimized to provide enhanced flow and coverage of the C4s. Other key properties, such as shelf life, thermal stability, solvent and moisture resistance, and adhesion to various surfaces, are addressed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An overview and evaluation of anisotropically conductive adhesive films for fine pitch electronic assembly

    Publication Year: 1993 , Page(s): 828 - 835
    Cited by:  Papers (17)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    Anisotropically conductive adhesive films (ACAFs), which provide electrical as well as mechanical interconnections for fine pitch applications, are discussed. The conductivity of ACAF materials is only in the Z-direction (perpendicular to the plane of the board), and electrical isolation is maintained in the X-Y plane. Currently, at least 15 ACAF materials are commercially available. The authors have developed a methodology for evaluating these materials for their mechanical and electrical properties and interconnection use in the 8 to 15-mil pitch range. In addition they characterized the materials according to their physical properties and cure characteristics. They detail the findings with a comparison of physical form to assembly/cure and final electrical properties. Data from scanning electron microscopy, thermal analysis of the ACAFs, and cure and assembly studies on mixed substrate test vehicles are included. Information on initial electrical testing and long-term reliability testing is given View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An 820 pin PGA for ultralarge-scale BiCMOS devices

    Publication Year: 1993 , Page(s): 893 - 901
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (828 KB)  

    A high-pin-count, high-performance pin grid array (PGA) has been developed for future ASIC devices using half-micron BiCMOS technology and having a maximum usable gate count of 300k. The package has been designed with due consideration of all package functions, electrical, thermal, and mechanical. A surface mount type pin joint was adopted to realize high wiring density on the printed wiring board. The package has 820 pins with a 50-mil pitch and five rows. A highly accurate tape automated bonding (TAB) technology was applied to the die assembly to achieve narrow pitch and high pad count for the bonding between the die and the package. The thermal resistance from the die to the ambient is lower than 1.5°C/W at 1 m/s air flow velocity. The electrical parameters of the package were quantified. The high reliability of the package and surface mount type soldering has been confirmed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Rigorous electromagnetic modeling of chip-to-package (first-level) interconnections

    Publication Year: 1993 , Page(s): 876 - 883
    Cited by:  Papers (51)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    A methodology is presented for the rigorous electromagnetic analysis of pulse transmission through first-level interconnects. The methodology combines a full-wave, vectorial, time-dependent Maxwell's equations solver with SPICE circuit models for the nonlinear drivers, to facilitate the accurate modeling of the electromagnetic phenomena occurring at the chip-to-package interface. Comparisons of the results obtained using this method with others calculated using SPICE simulations are used to validate the method and demonstrate its application in the electromagnetic modeling of high-speed packaging structures View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accelerated life test of Z-axis conductive adhesives

    Publication Year: 1993 , Page(s): 836 - 842
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    The success of coarse-pitch applications of conductive particle-filled adhesives has increased the interest in using such adhesives in fine-pitch applications, such as flip-chip on-board interconnection. Since these materials contain metallic particles to conduct currents in the z-direction (i.e., perpendicular to the plane of circuit board), their propensity for metal migration is a concern. Accelerated temperature, humidity and bias (THB) tests have been applied to a group of materials designed for fine-pitch applications. The accelerated life test conditions were 85°C/85% RH at three different voltages: 10 V, 50 V, and 100 V. The studies were focused on the samples' time-to-failure as well as the associated conduction and failure mechanisms. The test results showed significant metal migrations, and enhanced electric field stresses (102 to 10 4 V/mm) are proposed as the driving force for failures View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Off-axis sensor rosettes for measurement of the piezoresistive coefficients of silicon

    Publication Year: 1993 , Page(s): 925 - 931
    Cited by:  Papers (20)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB)  

    Experimental calibration results for the piezoresistive coefficients of silicon as a function of temperatures are presented. Measurements have been performed using a test chip incorporating a new off-axis 0-45°-90° rosette design. This rosette requires the application of only uniaxial stress for measurement of the three individual piezoresistive coefficients of silicon: π11, π12, and π44. Of even greater potential import, this rosette yields inherently temperature compensated values of the coefficients π44 and πD=(π11 12). P-type off-axis rosettes have been characterized as a function of temperature, and values for the temperature dependencies of π44 and πD are reported. The coefficients π44 in p-type silicon and π D in n-type silicon are needed for an optimized stress sensor on (100) silicon View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Creep of solder interconnects under combined loads

    Publication Year: 1993 , Page(s): 794 - 798
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    An exact analysis is presented for the creep deformation of solder interconnects subjected to the actions of bending moment and axial force. Dimensionless interaction curves and charts which relate the variables, axial force, location of neutral-axis, maximum bending stress and strain rate, bending moment and change in curvature rate are provided for engineering practice convenience. The tangent-modulus buckling loads of centrally loaded solder columns and a simple formula for the critical time to buckling are determined. The constitutive relationship of the solder interconnects is given View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interactive thermal modeling of electronic circuit boards

    Publication Year: 1993 , Page(s): 978 - 985
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    The numerical modeling of printed circuit board (PCB) configurations is addressed. Determining an optimal PCB design typically requires modeling and testing several different chip configurations. At present, much of the time and cost spent modeling these various configuration is repetitive in nature, with the same chip or board being regenerated several times before obtaining the most efficient design. By using a decoupled, iterative, numerical technique, a more systematic and efficient method for determining PCB temperature distributions has been developed and incorporated into a controlling algorithm which utilizes any standard finite-element code. Steady-state temperature distributions are obtained for each decoupled chip/board component by iterating upon decoupled interface boundary conditions until convergence is obtained. The main advantages of this decoupling technique are the elimination of repetitive numerical-model generation and the high level of interactive design provided View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Physical design alternatives for RISC workstation packaging

    Publication Year: 1993 , Page(s): 996 - 1005
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (920 KB)  

    A comparative study of packaging architectures for state-of-the-art multichip workstation-level reduced instruction set computers (RISCs) is presented. Single-chip on high-density printed wiring board packaging and several multichip module (MCM) strategies on ceramic and silicon substrate are included. These approaches are assessed, given current state-of-the-art manufacturing capabilities and projections for the foreseeable future. The study was conducted with AUDiT Version 4.2, a simulation tool for evaluating the physical design of electronic systems. The model RISC workstation was derived from a commercial computer. Good performance correlations between predicted data and this commercial workstation were obtained. The best performance in each case is obtained close to the tiling limit of the packages, or chips, for single chip, or multichip, modules, respectively. Results also show that the performance boundaries between alternative packaging architectures become blurred. Guidelines for improving each packaging architecture are given View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development of a cost-effective high-performance metal QFP packaging system

    Publication Year: 1993 , Page(s): 902 - 908
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    The design and development of MQUAD technology is described. The MQUAD packaging system is a high-performance, reliable technology currently in use for packaging of microprocessors and high-speed ASIC devices, including CMOS, BiCMOS, bipolar, gallium arsenide, and other high performance ICs. The packaging technology is being used for devices dissipating up to 14 W and switching speeds of up to 300 MHz. The design and development was carried out with the objectives of high thermal performance (up to 15 W); high electrical performance, with inductance and capacitances lower than those of comparable plastic quad flat packs (PQFPs); and reliability superior to that of the PQFPs. The approach taken was to use an adhesively bonded metal package. Reliability tests performed included temperature cycling, thermal shocks, solvent resistance, flammability, pressure cooker, and vapour phase shocks. Electrical characterization included θja and θ jc and resistance, inductance, and capacitance measurements View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Packaging and reliability of photonic components for subscriber network systems

    Publication Year: 1993 , Page(s): 778 - 782
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    The packaging of photonic components employing planar lightwave circuits (PLCs, optical waveguides on a silicon substrate) and UV-curable epoxy adhesives for use in optical subscriber network systems is described. UV curable adhesives with high humidity durability and small gravity change under high temperature conditions have been developed for assembling PLC components and I/O fibers. Reliability test results on two types of photonic integrated components-an optical coupler module and wavelength-division multiplexing (WDM) optical transmitter/receiver module-are described. The modules exhibit good stability during high humidity stress tests at 70°C and 90% relative humidity or 2500-cycle temperature cycle tests between -20°C and 80°C. The dark current of the photodiode in the assembled WDM optical module showed no significant increase and was well suppressed under 1 nA during 1000 h of test, showing that the use of adhesives does not reduce the long-term reliability of active components View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High performance optical datalink array technology

    Publication Year: 1993 , Page(s): 783 - 788
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    Demands for increased interconnection density and higher bandwidth, coupled with the stringent cost constraints of advanced wide-bandwidth telecommunication switching and high-throughput computer architectures, are exhausting conventional electrical interconnection capabilities. Presently, a bottleneck occurs at the board-to-board level of the interconnection hierarchy. A parallel optical interconnection technique called the one-dimensional optical data link (1D-ODL) is proposed to address this problem. It can be incorporated into system designs beginning at this interconnection level and beyond. The strategic insertion of parallel optical interconnection technology into these electronic processing systems not only meets projected performance requirements, but potentially offers them at a competitive cost View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Morphology and adhesion strength in electroless Cu metallized AlN substrate

    Publication Year: 1993 , Page(s): 1012 - 1020
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (812 KB)  

    The metallization of aluminum nitride substrates by electroless copper plating is investigated. The AlN substrate is etched by 4% NaOH to study the correlation between the adhesion strength and the surface roughness of etched AlN substrate. Both the as-received nonpolished and the polished AlN are studied. For the nonpolished substrate, the adhesion strength increases from 130 kg/cm2 for the sample with an average surface roughness of 0.2 μm to 230 kgf/cm2 for one with an average surface roughness of 0.82 μm. For the polished substrate, the adhesion strength reaches 271 kg/cm2 with a surface roughness of 0.19 μm. Mechanical interlocking is the major cause for the adhesion strength between the Cu and AlN substrates. The polished substrate that was subsequently etched could form fine cavities on the AlN surface, and the microetching effect resulted in a stronger mechanical interlocking, which increases the adhesion strength View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A package analysis tool based on a method of moments surface formulation

    Publication Year: 1993 , Page(s): 884 - 892
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    A package analysis tool that is based on a method of moments analysis and surface formulation is described. The surface formulation replaces ideal conductors by electric currents on their surfaces, while electric and magnetic currents are used for lossy conductors. These currents are then discretized using triangular linear current approximations, with the primary advantage of being able to represent arbitrary shapes. Frequency-dependent inductance and resistance are computed. The capacitance is also computed using piecewise-constant charge distributions on each triangle. The current and charge distributions are compatible, and therefore transmission line modeling can be done accurately. The algorithm allows use of the tool for both transmission line and discontinuity modeling, as well as analysis of simultaneous switching noise. The tool has a graphical pre- and postprocessor, which allows analysis of highly irregular structures, are found in most practical packaging configurations. An analysis of simultaneous switching noise for a 304-lead, six-layer single-chip module is presented as an example View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Anisotropically conductive polymer films with a uniform dispersion of particles

    Publication Year: 1993 , Page(s): 972 - 977
    Cited by:  Papers (7)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    Anisotropically conductive films consisting of a single layer of magnetically separated conductor spheres in a polymer matrix are described. In a vertical magnetic field, ferromagnetic spheres in a viscous medium become parallel magnetic dipoles and repel one another to produce a uniform, two-dimensional particle distribution. This structure is then frozen in by cooling or curing of the polymer matrix. In order to prevent the formation of undesirable dendritic particle protrusions, the magnetic force on the particles has to be balanced against the surface tension of the polymer and the gravity effect. As an interconnection material placed between circuit devices, the present conductive polymer films with uniformly distributed particles exhibit, as compared to the conventional, random distribution, a reduced tendency for electrical shorts and pad-to-pad variations in contact resistance values especially for fine pitch interconnections. Since the percolation stringers are no longer present in the magnetically distributed structure, it is anticipated that electric-field-induced isolation failures observed in some adhesive films will be substantially diminished View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electrical, structural and processing properties of electrically conductive adhesives

    Publication Year: 1993 , Page(s): 843 - 851
    Cited by:  Papers (31)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    There is growing interest in the potential of electrically conductive metal-loaded polymer adhesives. Eight commercial electrically conductive adhesive pastes for solder replacement in surface mount technology (SMT) and other microelectronic applications were selected for study, including both thermosetting and thermoplastic examples. All were silver based, except for one nickel-polymer composite. The properties on which this work was focused were the microstructure and electrical characteristics, with the specific purpose of determining the conduction mechanisms. The electrical measurements established that the primary source of electrical resistance is in the silver particles, with negligible contact effects between them. Differential scanning calorimetry results indicated that drifts in the electrical properties are not attributable to incomplete cures. Electrical measurements on simplified structures prepared in the laboratory are also reported View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Encapsulants used in flip-chip packages

    Publication Year: 1993 , Page(s): 858 - 862
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    A systematic approach to quantifying the viscosity and flow coverage, thermal expansion, modulus, glass transition temperature, filler size, alpha activity, adhesion, ionics content, fracture toughness, and electrical properties of low-thermal-expansion encapsulants is presented. The various test methods and their relevant technical aspects are discussed. Results achieved on a few selected materials are presented as examples View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Correlation of analytical and experimental approaches to determine thermally induced PWB warpage

    Publication Year: 1993 , Page(s): 986 - 995
    Cited by:  Papers (16)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (884 KB)  

    Thermomechanical design effects in the printed wiring board (PWB) design process are considered, In particular, a research project for developing advanced finite-element method (FEM)-oriented capabilities to simulate thermally induced PWB warpage is reported. The FE analysis results are validated by correlating them with measurements obtained from a separate experimental approach using the shadow Moire method View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A study on insertion loss improvement for an optical connector using the analysis of transmitted optical intensity

    Publication Year: 1993 , Page(s): 768 - 777
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    In one of the proposed methods for single-mode fiber connection the technique for stepwise orientation of the ferrule is used to reduce the transverse offset between butt-joint fiber cores by achieving the minimizing loss region (MLR). This method requires several stepwise rotations to make the fiber core within the MLR, which is determined by the optimal tradeoff between insertion loss and working time. In this method the insertion loss severely depends on the size of the predetermined MLR. A new assembly method through which a very small MLR can be achieved in a short time is proposed. With this method, performance can be in proved by minimizing misalignment offset of components without any requirement of strict tolerances. The eccentricity between the cladding and the core, which is classified as an intrinsic misalgnment factor, can be overcome. The rotating ferrule adjustment method, by using an adaptive control algorithm, makes the optimal peak intensity point fall into the very narrow MLR with just one try. Lower coupling loss can be achieved by aligning the peak intensity point in a very narrow region of the sleeve. An automated termination process can be setup, using a computer that performs both the power intensity distribution image process and orientation adjustment View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluation of a three-dimensional memory cube system

    Publication Year: 1993 , Page(s): 1006 - 1011
    Cited by:  Papers (14)  |  Patents (44)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    Silicon cubes consisting of 18-20 1-Mb DRAM chips have been fabricated. In the stacking process, the chips are joined by adhesive to form the cube, interconnected by chip metallization processes, and packaged on a ceramic pin grid array (PGA) substrate that is mounted onto a memory card for testing. Modification of an existing memory card permits the substrate with cube to be substituted in place of an array of 1-Mb DRAM memory modules that normally form the card array. Memory tube operation is verified by testing both original and cube memory cards on the same memory tester. Electrical signals for each of the cards are observed and compared. Extensive electrical modeling and simulation of the cube interconnect circuitry including the chip transfer metal, interchip bus lines, and PGA substrate were performed as part of the design and later verified. A high degree of interconnect and wiring redundancy was used to guarantee connection of all the chips in the cube to the applied control signals and data lines View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Attachment reliability evaluation and failure analysis of thin small outline packages (TSOP's) with Alloy 42 leadframes

    Publication Year: 1993 , Page(s): 961 - 971
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (948 KB)  

    A series of studies designed to evaluate the long term surface mount reliability of Alloy 42 leaded thin small outline packages (TSOPs) using thermal cycling as an acceleration method is described. Visual inspections, pull strength, and scanning electron microscopy were used to characterize the solder joints. In addition, the solder plating, lead wetting, and aging characteristics were evaluated. Failure during thermal cycling was primarily caused by the coefficient of thermal expansion (CTE) mismatch between the package and the printed wiring board. By using acceleration factors based on solder joint strain energies induced by global and local mismatches during thermal cycling, the experimental results are extrapolated to various use conditions and life expectancies. The TSOP solder joint reliability depends on environmental conditions (cyclic temperature range, temperature maximum, and dwell time), board thickness and materials, product intended service life, and expected hazard rate limits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This Transaction ceased production in 1993. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope