# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 20 of 20

Publication Year: 2014, Page(s): C1
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2014, Page(s): C2
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• ### A Quadratic-Interpolated LUT-Based Digital Predistortion Technique for Cellular Power Amplifiers

Publication Year: 2014, Page(s):133 - 137
Cited by:  Papers (13)
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Baseband digital predistortion (DPD) is an efficient and low-cost method for linearizing a power amplifier (PA) in a wireless system using a modulation scheme with nonconstant envelope. The polynomial and the lookup table (LUT) predistortion schemes are two commonly used approaches. Both approaches require time to find the inverse characteristics of the PA to be predistorted. However, for DPD to b... View full abstract»

• ### A Broadband Low-Power Millimeter-Wave CMOS Downconversion Mixer With Improved Linearity

Publication Year: 2014, Page(s):138 - 142
Cited by:  Papers (5)
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This brief presents a broadband, low-local-oscillator (LO)-power, and low-dc-power millimeter-wave (MMW) downconversion mixer with improved linearity using TSMC 90-nm CMOS low-power (LP) process. By employing an active load in the bias network, the linearity of the mixer can be improved effectively. In addition, the conversion gain (CG) of the mixer at high LO power is also improved, whereas the C... View full abstract»

• ### An Analysis of Phase Noise in Realigned VCOs

Publication Year: 2014, Page(s):143 - 147
Cited by:  Papers (7)
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This brief presents an analysis of realigned voltage-controlled oscillators (VCOs) leading to an analytical expression for their phase noise (PHN), which is of more general validity than those currently available in the literature. This brief further discusses a phenomenon that seems to have been given little attention, i.e., the increase by 3 dB of the high-frequency part of the PHN of a realigne... View full abstract»

• ### Combined Three-State/PWM Signal Coding for Wideband High-Efficiency Class-S Amplifiers

Publication Year: 2014, Page(s):148 - 152
Cited by:  Papers (1)
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A three-state signal coding scheme was recently proposed by the author for driving Class-S amplifiers with higher efficiency than conventional techniques. The magnitude is controlled by a timing code that specifies positive and negative rectangular pulses as well as a third zero state. High efficiency is attained when the active pulse widths are a half-cycle of the carrier frequency, and the zero ... View full abstract»

• ### A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth

Publication Year: 2014, Page(s):153 - 157
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A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While using only the ILO has intrinsic two dependence problems (JTB versus deskew and JTB versus a voltage-controlled oscillator tuning range required for 1 uni... View full abstract»

• ### Influence of Noise on the Phase and Amplitude of Second-Order Oscillators

Publication Year: 2014, Page(s):158 - 162
Cited by:  Papers (9)
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We investigate noise effects in second-order oscillators described in terms of amplitude and phase. We show that phase noise in an oscillator is a convection-diffusion problem, i.e., noise is responsible for both phase diffusion and frequency shift. The magnitude of a noise-induced frequency shift depends on both the noise intensity and on the curvature of iscohrons, i.e., manifolds describing the... View full abstract»

• ### An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme

Publication Year: 2014, Page(s):163 - 167
Cited by:  Papers (9)
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An area-efficient CMOS time-to-digital converter (TDC) based on a pulse-shrinking scheme with an improved cyclic delay line is proposed to achieve low thermal sensitivity in this brief. First, by only thermally compensating the pulse-shrinking unit rather than all delay cells, a large number of compensated circuits could be removed to reduce costs, and the thermal sensitivity of the TDC was still ... View full abstract»

• ### Modeling of a MOS Ultralow Voltage Astable Multivibrator for Energy Harvesting

Publication Year: 2014, Page(s):168 - 172
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This brief describes a new application of an oscillator with the inductive coupling of the gates as an astable multivibrator that can work with a power supply as low as 40 mV. A model of the circuit is presented, and the theoretical behavior is compared with simulated results, showing good agreement. The circuit can be used in the energy harvesting process from low-voltage sources for autonomous s... View full abstract»

• ### Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating

Publication Year: 2014, Page(s):173 - 177
Cited by:  Papers (3)
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A technique is presented to prevent timing errors under transient noise by borrowing time over multiple stages and by compensating once by delaying the clock gating over multiple cycles from the time-borrowing detection point. A logic network is presented for programming the number of stages n, over which time borrowing is performed to trade off supply noise tolerance with a performance pen... View full abstract»

• ### Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology

Publication Year: 2014, Page(s):178 - 182
Cited by:  Papers (1)
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The time needed for processing serial code in programs has become the performance bottleneck of multicore computer systems according to Amdahl's law. A high-speed clock rate processor is essential for processing this serial code. The register file is the core component in high-performance processors due to its direct impact on the cycle per instruction of the CPU. This brief presents the design of... View full abstract»

• ### On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator

Publication Year: 2014, Page(s):183 - 187
Cited by:  Papers (5)
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In this brief, a new technique to measure the on-chip rise/fall delay of an individual gate is presented. In the proposed technique, the rise/fall gate delay is measured using the duty cycle of a reconfigurable ring oscillator (RRO). A set of linear equations is formed with the different configuration settings of the RRO, relating the rise/fall delay of all the gates in the path of the RRO to the ... View full abstract»

• ### Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors

Publication Year: 2014, Page(s):188 - 192
Cited by:  Papers (5)
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This brief proposes one-write-one-read (1W1R) and two-write-two-read (2W2R) multiport (MP) SRAMs for register file applications in nanoscale CMOS technology. The cell features a cross-point Write word-line structure to mitigate Write Half-Select disturb and improve the static noise margin (SNM). The Write bit-lines (WBLs) and Write row-access transistors are shared with adjacent bit-cells to reduc... View full abstract»

• ### A Split-Path Sensing Circuit for Spin Torque Transfer MRAM

Publication Year: 2014, Page(s):193 - 197
Cited by:  Papers (15)
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As process technology scales down, sensing becomes difficult during read operations because the supply voltage, i.e., VDD, decreases and the process variation increases. Thus, a high enough sensing yield cannot be obtained with a conventional sensing circuit in deep submicron process technology. In this brief, a split-path sensing circuit is proposed to achieve a large enough sensing margin by usi... View full abstract»

• ### New Improved Algorithms for Compressive Sensing Based on $\ell_{p}$ Norm

Publication Year: 2014, Page(s):198 - 202
Cited by:  Papers (12)
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A new algorithm for the reconstruction of sparse signals, which is referred to as the ℓp-regularized least squares ( ℓp-RLS) algorithm, is proposed. The new algorithm is based on the minimization of a smoothed ℓp-norm regularized square error with p <; 1 . It uses a conjugate-gradient (CG) optimization method in a sequential minimization str... View full abstract»

• ### A Simple Ladder Realization of Maximally Flat Allpass Fractional Delay Filters

Publication Year: 2014, Page(s):203 - 207
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This brief proposes a new ladder structure for the Thiran fractional delay filter (i.e., maximally flat allpass fractional delay filter given by the Thiran approximation). The proposed ladder structure is based on a continued fraction representation. Although there exists a similar approach that was proposed by Tassart and Depalle, their structure is not realizable because of delay-free loops. On ... View full abstract»

• ### Open Access

Publication Year: 2014, Page(s): 208
| |PDF (1156 KB)
• ### IEEE Circuits and Systems Society Information

Publication Year: 2014, Page(s): C3
| |PDF (118 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2014, Page(s): C4
| |PDF (108 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org