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Embedded Systems Letters, IEEE

Issue 1 • Date March 2014

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Displaying Results 1 - 10 of 10
  • Table of contents

    Page(s): C1
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  • IEEE Embedded Systems Letters publication information

    Page(s): C2
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  • Introduction of New Associate Editors

    Page(s): 1
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  • Guest Editorial: Special Issue on Rigorous Modeling and Analysis of Cyber-Physical Systems

    Page(s): 2 - 3
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  • An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis

    Page(s): 4 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (691 KB) |  | HTML iconHTML  

    Digital control systems are traditionally designed independent of their implementation platform, assuming constant sensor sampling rates and processor response times. Applications are deployed to processors that are shared amongst control and noncontrol tasks, to maximize resource utilization. This potentially overlooks that computing mechanisms meant for improving average CPU usage, such as cache, interrupts, and task management through schedulers, contribute to nondeterministic interference between tasks. This response time jitter can result in reduced system stability, motivating further study by both the controls and computing communities to maximize CPU utilization, while maintaining physical system stability needs. In this letter, we describe an field-programmable gate array (FPGA)-based embedded software platform coupled with a hardware plant emulator (as opposed to purely software-based simulations or hardware-in-the-loop setups) that forms a basis for safe and accurate analysis of cyber-physical systems. We model and analyze an inverted pendulum to demonstrate that our setup can provide a significantly more accurate representation of a real system. View full abstract»

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  • HLC-PCP: A Resource Synchronization Protocol for Certifiable Mixed Criticality Scheduling

    Page(s): 8 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1007 KB) |  | HTML iconHTML  

    Today's safety-critical Cyber-Physical Systems (CPS) often need to integrate multiple diverse applications with varying levels of importance, or criticality. Mixed-criticality scheduling (MCS) has been proposed with the objectives of achieving certification at multiple criticality levels and efficient utilization of hardware resources. Current work on MCS typically assumes tasks at different criticality levels are independent and do not share any resources (data). We propose highest-locker criticality, priority-ceiling protocol (HLC-PCP), which extends the well-known priority ceiling protocol (PCP) to be applicable to adaptive mixed-criticality (AMC), a variant of MCS. We present methods for worst-case blocking time computation with HLC-PCP, used for schedulability analysis of AMC with resource sharing. View full abstract»

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  • Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis

    Page(s): 12 - 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (781 KB) |  | HTML iconHTML  

    Resistive memory, also known as memristor, is recently emerging as a potential successor to traditional charge-based memories. However, the nanoscale features of these devices introduce challenges in modeling and simulation. In this paper, we propose a novel Verilog-A based complementary resistive switch memory model for effective simulation and analysis. Our proposed model captures desired nonlinear characteristics using voltage based state control as opposed to recently proposed current based state control. We demonstrate that such state control has advantages for our proposed CRS model based crossbar arrays in terms of symmetric ON/OFF voltages and significantly reduced sneak path currents with high noise margin compared to traditional memristor based architectures. Moreover, to validate the effectiveness of our Verilog-A based model we carry out extensive simulations and analyses for different crossbar array architectures using traditional EDA tools. View full abstract»

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  • Open Access

    Page(s): 16
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  • IEEE Embedded Systems Letters information for authors

    Page(s): C3
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  • [Blank page - back cover]

    Page(s): C4
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Aims & Scope

The IEEE EMBEDDED SYSTEMS LETTERS (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

Full Aims & Scope

Meet Our Editors

EDITOR-IN-CHIEF
Krithi Ramamritham
Department of Computer Science and Engineering
Indian Institute of Technology Bombay

DEPUTY EDITOR-IN-CHIEF
Catherine Gebotys
Department of Electrical and Computer Engineering
University of Waterloo