IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 3 • March 2014

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  • Table of contents

    Publication Year: 2014, Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2014, Page(s): C2
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  • Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems

    Publication Year: 2014, Page(s):329 - 342
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1027 KB) | HTML iconHTML

    Recently hybrid cache architecture consisting of both spin-transfer torque RAM (STT-RAM) and SRAM has been proposed for energy efficiency. In hybrid caches, migration-based techniques have been proposed. A migration technique dynamically moves write-intensive and read-intensive data between STT-RAM and SRAM to explore the advantages of hybrid cache. Meanwhile, migrations also introduce extra reads... View full abstract»

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  • Error Model Guided Joint Performance and Endurance Optimization for Flash Memory

    Publication Year: 2014, Page(s):343 - 355
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (618 KB) | HTML iconHTML

    As flash memory has better performance than hard disks, it has been widely applied in embedded systems, personal computers, and data centers as storage components. However, endurance and write performance are the two key challenges in the deployment of flash memory. In this paper, with the awareness of errors induced from write operations, endurance, and retention time, a stage-based optimization ... View full abstract»

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  • Fast Online Synthesis of Digital Microfluidic Biochips

    Publication Year: 2014, Page(s):356 - 369
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1247 KB) | HTML iconHTML

    We introduce an online synthesis flow, focusing primarily on the virtual topology and operation binder, for digital microfluidic biochips, which will enable real-time response to errors and control flow. The objective of this flow is to facilitate fast assay synthesis while minimally compromising the quality of results. In particular, we show that a virtual topology, which constrains the allowable... View full abstract»

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  • TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network

    Publication Year: 2014, Page(s):370 - 383
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (788 KB) | HTML iconHTML

    Dynamic partial reconfiguration of FPGAs enables the dynamic specialization of the circuit for the runtime needs of the application. Previously a tool flow, called the TLUT tool flow, was developed to aid the designer in applying dynamic circuit specialization (DCS) for their designs. The TLUT tool flow generates an implementation in which the lookup tables (LUTs) can be specialized during runtime... View full abstract»

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  • Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions

    Publication Year: 2014, Page(s):384 - 396
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1717 KB) | HTML iconHTML

    SRAM cells generally require an extremely low failure rate (i.e., high yield) in the per cell basis to ensure a reasonably moderate yield for the whole chip. Existing yield analysis methods still encounter issues related to multiple failure regions resulting from high-dimensional process parameter space and/or multiple performance specifications. This paper proposes a new method that combines the ... View full abstract»

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  • A Novel Layout Decomposition Algorithm for Triple Patterning Lithography

    Publication Year: 2014, Page(s):397 - 408
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (12562 KB) | HTML iconHTML

    While double patterning lithography (DPL) has been widely recognized as one of the most promising solutions for the sub-22 nm technology node to enhance pattern printability, triple patterning lithography (TPL) will be required for gate, contact, and metal-1 layers which are too complex and dense to be split into only two masks, for the 15 nm technology node and beyond. Nevertheless, there is very... View full abstract»

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  • A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

    Publication Year: 2014, Page(s):409 - 422
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9762 KB) | HTML iconHTML

    An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core contribution is a detailed-routing algorithm based on a Boolean formulation of the problem. The algorithm uses a novel encoding scheme, graph theory to support floating terminals... View full abstract»

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  • A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems

    Publication Year: 2014, Page(s):423 - 436
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1049 KB) | HTML iconHTML

    The clock buffer polarity assignment is one of the effective design schemes to mitigate the power/ground noise caused by the clock signal propagation in high-speed digital systems. This paper overcomes a set of fundamental limitations of the conventional clock buffer polarity assignment methods, which are: 1) the unawareness of the signal delay (i.e., arrival time) differences to the leaf clock bu... View full abstract»

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  • Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip

    Publication Year: 2014, Page(s):437 - 450
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2372 KB) | HTML iconHTML

    Photonic devices are widely used in optical networks-on-chip (ONoCs) and suffer from crosstalk noise. The accumulative crosstalk noise in large scale ONoCs diminishes the signal-to-noise ratio (SNR), causes severe performance degradation, and constrains the network scalability. For the first time, this paper systematically analyzes and models the worst-case crosstalk noise and SNR in folded-torus-... View full abstract»

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  • Pre-Silicon Bug Forecast

    Publication Year: 2014, Page(s):451 - 463
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (11968 KB) | HTML iconHTML

    The ever-intensifying time-to-market pressure imposes great challenges on the pre-silicon design phase of hardware. Before the tape-out, a pre-silicon design has to be thoroughly inspected by time-consuming functional verification and code review to exclude bugs. For functional verification and code review, a critical issue determining their efficiency is the allocation of resources (e.g., computa... View full abstract»

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  • Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs

    Publication Year: 2014, Page(s):464 - 475
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8790 KB) | HTML iconHTML

    Pre-bond known-good-die (KGD) test is necessary to ensure stack yield for the future adoption of 3-D integrated circuits. Die wrappers that contain boundary registers at the interface between dies have been proposed as a solution for KGD test. It has been shown in the literature that if gated scan flops (GSFs) are substituted for traditional scan flops in the boundary register, then both pre-bond ... View full abstract»

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  • Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs

    Publication Year: 2014, Page(s):476 - 488
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1795 KB) | HTML iconHTML

    This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First, we target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults), but also par... View full abstract»

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  • 2014 IEEE compound Semiconductor IC symposium

    Publication Year: 2014, Page(s): 489
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  • Publish your article in IEEE Access

    Publication Year: 2014, Page(s): 490
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  • Open Access

    Publication Year: 2014, Page(s): 491
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  • Together, we are advancing technology

    Publication Year: 2014, Page(s): 492
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2014, Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2014, Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu