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Computers, IEEE Transactions on

Issue 3 • Date March 1994

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Displaying Results 1 - 17 of 17
  • Comments on "Evaluation of A+B = K conditions without carry propagation

    Publication Year: 1994
    Cited by:  Papers (3)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (121 KB)  

    A special carry-free circuit for the evaluation of conditions of the type A+B=K is proposed by Cortadella and Llaberia (1992), and its usefulness for reducing the negative effects of conditional branches in pipelined architectures is noted. It is shown that the same advantages are offered by another equally simple circuit based on carry-save redundant numbers and (3, 2)-counters. This alternative circuit has other potential applications and much of it may in fact be already present in some ALU's.<> View full abstract»

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  • Comments on "Decomposition of complex multipliers using polynomial encoding"

    Publication Year: 1994 , Page(s): 381 - 383
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (303 KB)  

    Presents a better way of decomposition of complex multipliers using polynomial encoding than the method presented in the paper, "Decomposition of Complex Multipliers Using Polynomial Encoding." ibid., vol. 41, no. 10, p1331-3, 1992. The decomposition described in this paper makes use of smaller multipliers which results in smaller ROMs if ROM table look-ups are used to implement multipliers.<> View full abstract»

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  • Comments on "A characterization of binary decision diagrams"

    Publication Year: 1994 , Page(s): 383 - 384
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (153 KB)  

    Chakravarty presents a characterization of BDD's in terms of the complexity of some computational problems, ibid., vol. 42, p. 129-137, Feb. 1993. In these comments, some incorrectly stated restrictions on the "number of repeated variables" are corrected and results on the translation problem (to include EXOR and NEXOR gates) are generalized.<> View full abstract»

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  • High-performance 3-1 interlock collapsing ALU's

    Publication Year: 1994 , Page(s): 257 - 268
    Cited by:  Papers (13)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (980 KB)  

    A high-performance 3-1 interlock collapsing ALU, i.e., an ALU that allows the execution of most execution interlocks in a single machine cycle, is presented. We focus on reducing the Boolean equations describing the device and the incorporation of new mechanisms in the interlock collapsing ALU design. In particular, we focus on the reduction of the critical path, regarding delay, for the interlock collapsing ALU implementation. It is shown that the delay associated with the implementation of the proposed device, in terms of logic stages, assuming a commonly available CMOS technology, is equivalent to the number of logic stages required for the implementation of a 3-1 binary adder. The resulting implementation demonstrates that the proposed 3-1 interlock collapsing ALU can be designed to outperform existing schemes for interlock collapsing ALU's by a factor of at least two. Finally, it is suggested that the proposed device can be used in the implementation of multiple instruction issuing machines, allowing the issuance and execution of interlocks in parallel and in a single machine cycle with no cycle time increases View full abstract»

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  • Over-redundant digit sets and the design of digit-by-digit division units

    Publication Year: 1994 , Page(s): 269 - 277
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (860 KB)  

    Over-redundant digit sets are defined as those ranging from -s to +s, with s⩾B, B being the radix. This paper presents new techniques for the direct computation of division, that use an over-redundant digit set for representing the quotient, instead of simply redundant ones used previously. In particular, general criteria for synthesizing the digit selection rules and remainder updating are given for any radix and index of redundancy. A methodology combining the use of over-redundant digit sets with the prescaling of the divisor is also studied in order to achieve radix-B division units with trivial digit selection functions. It is also shown, for the specific case of radix-4 that using a prescaling slightly wider than in a radix-4 unit by M.D. Ercegovac and T. Lang (1990) possible to avoid the digit selection table. The paper also presents a modified algorithm for on-the-fly conversion of the result into the irredundant form. The proposed methodology can be considered as an alternative to existing division techniques View full abstract»

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  • Error correcting codes over Z2(m) for algorithm-based fault tolerance

    Publication Year: 1994 , Page(s): 370 - 374
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    Algorithm-based fault tolerance is a scheme of low-cost error protection in real-time digital signal processing environments and other computation-intensive tasks. In this paper, a new method for encoding data is proposed and, furthermore, two kinds of error-correcting codes over Z2(m), which can be used with fixed-point arithmetic in practical algorithm-based fault tolerant systems, are introduced View full abstract»

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  • Conflict resolution and fault-free path selection in multicast-connected cube-based networks

    Publication Year: 1994 , Page(s): 374 - 380
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    Presents an algorithm that solves the conflict resolution problem in fault-tolerant multicast-connected MINs. Without loss of generality, the authors apply the algorithm to reconfigure a four-path cube-based network. An intensive simulation study is conducted to reveal the performance improvement gained by the conflict resolution and fault-free path selection algorithm on the network under study. The simulation results indicate that the probability of failure to provide multicast connections using two paths is comparable to that of using three and four paths under various fault scenarios. The results also indicate that an effective reconfiguration algorithm based on two alternate paths has a great impact on the network performance in the presence of faults and conflicts View full abstract»

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  • Almost sure diagnosis of almost every good element [logic testing]

    Publication Year: 1994 , Page(s): 295 - 305
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (984 KB)  

    We demonstrate a structure for mutual test among N processing elements. We indicate how this structure might be used to identify the good dice on a semiconductor wafer at a cost below that of current techniques. Under either a digraph or a comparison model, our proposed test structure has the following properties: 1) It is nearly regular. 2) It can be laid out in area O(⊖(n). 3) In time ⊖(N) and with high probability, all but at most an arbitrarily small fraction of the good elements can be identified. 4) The number of tests or comparisons per element is bounded by a constant. We approximate this constant analytically. The result is a substantial savings over the ⊖(log N) tests per element in regular structures whose purpose is to identify, with high probability, every good element. In contrast with the majority of previous work, our results apply even when less than half of the elements are good View full abstract»

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  • Computing display conflicts in string visualization

    Publication Year: 1994 , Page(s): 350 - 361
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1148 KB)  

    Strings are used to represent a variety of objects such as DNA sequences, text, and numerical sequences. A model for a system for the visualization and analysis of strings was proposed by D. Mehta and S. Sahni (1992). The problem of display conflicts that arise in this model was identified and methods to overcome it were suggested. These methods require the computation of display conflicts. We present efficient algorithms to compute display conflicts View full abstract»

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  • Testing finite-state machines: state identification and verification

    Publication Year: 1994 , Page(s): 306 - 320
    Cited by:  Papers (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1604 KB)  

    We study the complexity of two fundamental problems in the testing of finite-state machines. 1) Distinguishing sequences (state identification). We show that it is PSPACE-complete to determine whether a finite-state machine has a preset distinguishing sequence. There are machines that have distinguishing sequences, but only of exponential length. We give a polynomial time algorithm that determines whether a finite-state machine has an adaptive distinguishing sequence. (The previous classical algorithms take exponential time.) Furthermore, if there is an adaptive distinguishing sequence, then we give an efficient algorithm that constructs such a sequence of length at most n(n-1)/2 (which is the best possible), where n is the number of states. 2) Unique input output sequences (state verification). It is PSPACE-complete to determine whether a state of a machine has a unique input output sequence. There are machines whose states have unique input output sequences but only of exponential length View full abstract»

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  • Some additions to “solution of switching equations based on a tabular algebra”

    Publication Year: 1994 , Page(s): 365 - 367
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    A method was presented by A.L. Ruiz, P.P. Trabado, and J.O. Lopera (see ibid., vol.42, no. 5, p. 591-6, 1993) for efficiently generating the solutions of Boolean equations by using tables (i.e., rectangular arrays or matrices) of 0's, 1's, and dashes to represent Boolean expressions. Some enhancements of their method are presented. First, it is shown how the uniting theorem can be applied directly to simplify tables. Then it is shown how to complement a table, which would make their method (henceforth referred to as RTL) directly applicable to expressions containing complemented subexpressions. The latter result allows the method to be extended from the solution of equations of the form f(X)=1 to equations of the form f(X)=0, and, more generally to equations of the form f(X)=g(X), or to simultaneous equations of the same types View full abstract»

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  • Safe system level diagnosis

    Publication Year: 1994 , Page(s): 367 - 370
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    A new approach called safe system level diagnosis is proposed. With this approach, in the event of a small number of faults, all the faulty nodes can be identified; also, in the event of a large number of faults, the fault condition can be detected. Systems which achieve a specified level of safe diagnosis are characterized and a diagnosis algorithm for such systems is presented. Also, an application of safe diagnosis to adaptive diagnosis on arbitrary t-diagnosable graphs is discussed View full abstract»

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  • Perfect shifters [multiprocessor interconnection networks]

    Publication Year: 1994 , Page(s): 340 - 349
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    Pin-efficient single-instruction multiple-data networks, with p≈√(2m) pins per cell that can-in one clock tick-shift data by any amount k in an interval [-m,m] are considered. Perfect barrel shifters, which perform the group of permutations c→c+k(mod n), 0⩽k⩽n-1, using p=q+1 pins per cell, are known to exist for all n=q2+q+1, where q is any prime power. In sharp contrast, it is shown that for any permutation π of order greater than 3m, one-tick perfect shifters for the set of permutations π[-m,m] ={πk|-m⩽k⩽m} exist only for the three cases (m=1, p=2), (m=3, p=3), and (m=6, p=4). In particular, only three perfect linear arrays, c→c+k, exist. The proof is based on a relationship between the difference covers and zero-one solutions to certain quadratic equations View full abstract»

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  • Design of efficient balanced codes

    Publication Year: 1994 , Page(s): 362 - 365
    Cited by:  Papers (26)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    All words in a balanced code have equal number of ones and zeros. Denote by DC(n,k) a balanced (or dc-free) code of length n, and 2k code words. We design an efficient DC(k+r, k) code with k=2r+1-0.8√(r-2). These codes are optimal up to the construction method, introduced by D.E. Knuth (1986) View full abstract»

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  • Guaranteeing synchronous message deadlines with the timed token medium access control protocol

    Publication Year: 1994 , Page(s): 327 - 339
    Cited by:  Papers (57)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1180 KB)  

    We study the problem of guaranteeing synchronous message deadlines in token ring networks where the timed token medium access control protocol is employed. Synchronous bandwidth, defined as the maximum time for which a node can transmit its synchronous messages every time it receives the token, is a key parameter in the control of synchronous message transmission. To ensure the transmission of synchronous messages before their deadlines, synchronous capacities must be properly allocated to individual nodes. We address the issue of appropriate allocation of the synchronous capacities. Several synchronous bandwidth allocation schemes are analyzed in terms of their ability to satisfy deadline constraints of synchronous messages. We show that an inappropriate allocation of the synchronous capacities could cause message deadlines to be missed, even if the synchronous traffic is extremely low. We propose a scheme, called the normalized proportional allocation scheme, which can guarantee the synchronous message deadlines for synchronous traffic of up to 33% of available utilization View full abstract»

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  • A parallel algorithm for reconfiguring a multibutterfly network with faulty switches

    Publication Year: 1994 , Page(s): 321 - 326
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    This paper describes a deterministic algorithm for reconfiguring a multibutterfly network with faulty switches. Unlike previous reconfiguration algorithms, the algorithm is performed entirely by the network, without the aid of any off-line computation, even though many of the switches may be faulty. The algorithm reconfigures an N-input multibutterfly network in O(logN) time. After reconfiguration, the multibutterfly can tolerate f worst-case faults and still route any permutation between some set of N-O(f) inputs and N-O(f) outputs in O(log N) time View full abstract»

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  • Fast hardware-based algorithms for elementary function computations using rectangular multipliers

    Publication Year: 1994 , Page(s): 278 - 294
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1264 KB)  

    As the name suggests, elementary functions play a vital role in scientific computations. Yet due to their inherent nature, they are a considerable computing task by themselves. Not surprisingly, since the dawn of computing, the goal of speeding up elementary function computation has been pursued. This paper describes new hardware based algorithms for the computation of the common elementary functions, namely division, logarithm, reciprocal square root, arc tangent, sine and cosine. These algorithms exploit microscopic parallelism using specialized hardware with heavy use of truncation based on detailed accuracy analysis. The contribution of this work lies in the fact that these algorithms are very fast and yet are accurate. If we let the time to perform an IEEE Standard 754 double precision floating point multiplication be τ×, our algorithms to achieve roughly 3.68τ×,4.56τ×, 5.25τ×, 3.69τ×, 7.06τ×, and 6.5τ×, for division, logarithm, square root, exponential, are tangent and complex exponential (sine and cosine) respectively. The trade-off is the need for tables and some specialized hardware. The total amount of tables required, however, is less than 128 Kbytes. We discuss the hardware, algorithmic and accuracy aspects of these algorithms View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org