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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb. 2014

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Displaying Results 1 - 19 of 19
  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Semiconductor Manufacturing publication information

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  • Process-Machine Interaction (PMI) Modeling and Monitoring of Chemical Mechanical Planarization (CMP) Process Using Wireless Vibration Sensors

    Page(s): 1 - 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1335 KB) |  | HTML iconHTML  

    We present a deterministic process-machine interaction (PMI) model that can associate different complex time-frequency patterns, including nonlinear dynamic behaviors that manifest in vibration signals measured during a chemical mechanical planarization (CMP) process for polishing blanket copper wafer surfaces to near-optical finish (Ra ~ 5 nm) to specific process mechanisms. The model captures the effects of the nonuniform structural properties of the polishing pad, pad asperities, and machine kinematics on CMP dynamics using a deterministic 2 ° of freedom nonlinear differential equation. The model was validated using a Buehler (Automet 250) bench top CMP machine instrumented with a wireless (XBee IEEE 802.15.4 RF module) multi-sensor unit that includes a MEMS 3-axis accelerometer (Analog Devices ADXL 335). Extensive experiments suggest that the deterministic PMI model can capture such significant signal patterns as aperiodicity, broadband frequency spectra, and other prominent manifestations of process nonlinearity. Remarkably, the deterministic PMI model was able to explain not just the physical sources of various time-frequency patterns observed in the measured vibration signals, but also, their variations with process conditions. The features extracted from experimental vibration data, such as power spectral density over the 115-120 Hz band, and nonlinear recurrence measures were statistically significant estimators (R2 ~ 75%) of process parameter settings. The model together with sparse experimental data was able to estimate process drifts resulting from pad wear with high fidelity (R2 ~ 85%). The signal features identified using the PMI model can lead to effective real-time in-situ monitoring of wear and anomalies in the CMP process. View full abstract»

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  • Analysis of Junction Leakage Current Failure of Nickel Silicide Abnormal Growth Using Advanced Transmission Electron Microscopy

    Page(s): 16 - 21
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    This is the first paper to reveal the formation mechanism of the abnormal growth of nickel silicide that causes leakage-current failure in complementary metal-oxide- semiconductor (CMOS) devices by using advanced transmission electron microscope (TEM) techniques: electron tomography and spatially-resolved electron energy-loss spectroscopy (EELS). We reveal that the abnormal growth of Ni silicide results in a single crystal of NiSi2 and that it grows toward Si <;110> directions along (111) planes with the Ni diffusion through the silicon interstitial sites. In addition, we confirm that the abnormal growth is related to crystal microstructure and crystal defects. These detailed analyses are essential to understand the formation mechanism of abnormal growths of Ni silicide. View full abstract»

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  • Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs

    Page(s): 22 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (30063 KB) |  | HTML iconHTML  

    This paper proposes a novel fast and unified mixed-signal design methodology by incorporating manufacturing process variation awareness in power, performance, and parasitic optimization. The design of a process variation aware voltage controlled oscillator (VCO) at nano-CMOS technologies is demonstrated as a case study. Through accurate simulations it is shown that process variations have a drastic effect on performance metrics such as the center frequency of the VCO. In the presence of worst-case process variation, performance optimization of the VCO is applied, along with a dual-oxide technique for power minimization. The final product of the proposed process-variation aware methodology is an optimal physical design. The proposed methodology achieves 25% power reduction (including leakage) with only 1% degradation in center frequency compared to the target, in the presence of worst-case process variation and parasitics, with a 41% area penalty. View full abstract»

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  • Analysis of Plating Solutions Used in the Microelectronic Manufacturing Process Employing Capillary Electrophoresis

    Page(s): 32 - 37
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    Capillary electrophoresis (CE) is found to be suitable for determining the concentration of inorganic ions in the copper and gold plating solutions used in the semiconductor manufacturing process. Tris(hydroxymethyl) aminomethane (Tris buffer) with added pyridine dicarboxylic acid (PDC) allows the simultaneous detection of sulfate and copper ions, and adding chromate allows the separation of Cl- from the sulfate matrix. When the methods developed are applied to process chemicals, the new analytical technique agrees well with that of current standard techniques within 99.5% (±0.99). The detection limits of these inorganic ions ranged from 0.99 to 2.32 μg/mL, with relative standard deviations (n=4) ranging from 0.38% to 10.3%. A method to separate sulfite from sulfate was also developed for gold plating solutions. The optimized method successfully permits determination of sulfite and sulfate with concentrations of 4.65% (±0.43) and 4.32% (±0.37), respectively. These methods can lower production cost, raise production efficiency, and increase the chemical lifetime in the semiconductor manufacturing process through simplified process control, waste reduction, and recycling. View full abstract»

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  • Study and Improvement on Tungsten Plug Corrosion in CMP Process for PCRAM

    Page(s): 38 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7442 KB) |  | HTML iconHTML  

    To reduce the reset current for developing reliable high density phase change random access memory (PCRAM), small bottom electrode contact (BEC) size formation is a critical process. One of the failure mode for the process is the corrosion of tungsten plug, which is caused by tungsten chemical mechanical planarization (CMP) process. In this paper, this CMP process was analyzed. The tungsten polishing step process was characterized by the coefficient j and it shows good performance in tungsten polishing process. The alkali and acidic buff slurry effect on tungsten plug performance were studied. The result shows that the recess free tungsten plug had been fabricated with acidic buff slurry. The electric results confirm that it can fulfill the set operation of PCRAM cells. View full abstract»

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  • A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO

    Page(s): 43 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (908 KB) |  | HTML iconHTML  

    This paper presents a novel design methodology for design of optimal and robust current starved voltage controlled oscillator (CSVCO) circuit. A recently developed multiobjective optimization technique infeasibility driven evolutionary algorithm is used to minimize the power and the phase noise of the circuit at its schematic and physical level. The multiobjective optimization is carried out by taking into account the extracted parasitics that would be present in the physical integrated circuit and the random variations of parameters during fabrication in foundry. This method helps the designer in semiconductor industry by effectively reducing several time consuming design iterations to a single iteration ensuring the near optimal performance of the CSVCO. The performance of the circuit is validated by carrying out simulations for transient and noise analysis in Cadence tools using 90 nm 1P9M CMOS process. View full abstract»

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  • Modeling and Experimental Study of the Kink Formation Process in Wire Bonding

    Page(s): 51 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1373 KB) |  | HTML iconHTML  

    Looping is a key technology for the modern wire bonder. A kink is a critical structure in a wire loop. In order to understand the kink formation mechanism, a 2-D dynamic finite element model is developed using ANSYS/LS-DYNA, in which the air tension force, friction between capillary and wire, and real capillary trace are considered. The simulated kink formation process was verified by an experiment. With this model, the strain distribution on a gold wire was calculated, and the effects of wire material properties and capillary trace parameters on the kink number, position, and loop profiles were studied. Simulation results show that a minute average plastic strain of 0.14 is needed to form a distinct kink in a wire. Similarly, an elastic core with an average plastic strain of less than 0.08 at the center of a kink provides stiffness and sag/sway resistance for loops. A kink is a wire segment with plastic deformation outside and an elastic core inside, and the number of kinks and their positions are mainly affected by the capillary trace. In contrast, wire material properties only slightly influence the kink properties. This paper may provide helpful insights into loop design for modern microelectronics packages. View full abstract»

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  • Compensating Modeling Overlay Errors Using the Weighted Least-Squares Estimation

    Page(s): 60 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (295 KB) |  | HTML iconHTML  

    The lithography performed on a stepper is a key process of integrated circuit manufacturing. To have a better resolution and alignment accuracy in lithography, it is important to model the overlay errors and compensate them into tolerances. The systematic overlay errors are commonly modeled as the sum of inter-field and intra-field errors. The inter-field errors describe the global effect, while the intra-field errors indicate the local effect. In this paper, two overlay error models are introduced, and a weighted least-squares (WLS) estimator is developed to derive the more accurate linear term parameters of the overlay errors. The least-squares (LS) estimator is applied to the Arnold ten-parameter model for estimating the parameters of linear and nonlinear terms. We intend to estimate the parameters of a linear term, while taking the nonlinear term as our modeling residual errors. Then, we use the WLS estimator to derive the more accurate linear term parameters in the Perloff eight-parameter model. Finally, the WLS estimator is applied to real data collected from 453 wafers provided by a wafer fabrication facility in Taiwan. Test results demonstrate that the linear term parameters estimated by the WLS estimator are much more accurate than those obtained by the LS estimator. View full abstract»

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  • Data Mining for Optimizing IC Feature Designs to Enhance Overall Wafer Effectiveness

    Page(s): 71 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1042 KB) |  | HTML iconHTML  

    As global competition continues to strengthen in semiconductor industry, semiconductor companies have to continuously advance manufacturing technology and improve productivity to maintain competitive advantages. Die cost is significantly influenced by wafer productivity that is determined by yield rate and the number of gross dies per wafer. However, little research has been done on design for manufacturing and productivity enhancement through increasing the gross die number per wafer and decreasing the required shot number for exposure. This paper aims to propose a novel approach to improve overall wafer effectiveness via data mining to generate the optimal IC feature designs that can bridge the gap between integrated circuit (IC) design and wafer fabrication by providing chip designer with the optimal IC feature size in the design phase to increase gross dies and reduce the required shots. An empirical study was conducted in a leading semiconductor company for validation. The results have shown that the proposed approach can effectively enhance wafer productivity. Indeed, the developed solution has been implemented in the company to provide desired IC features to IC designers to enhance overall wafer effectiveness. View full abstract»

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  • Robust Relevance Vector Machine With Variational Inference for Improving Virtual Metrology Accuracy

    Page(s): 83 - 94
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1046 KB) |  | HTML iconHTML  

    Virtual metrology (VM) technology is an efficient and effective method of online and wafer-to-wafer process monitoring. It is realized by constructing a prediction model between real-time equipment sensor data and the quality characteristics of wafers that should be measured. The most commonly employed prediction method for VM is a neural network (NN) approach due to its flexibility and fast computation time. However, it can easily suffer from the overfitting problem and is affected by naturally occurring potential outlying observations contained in given data. Moreover, it does not provide prediction intervals for future observations that can be used to detect abnormal process problems. In this paper, an advanced prediction model for VM is developed to resolve these issues. The proposed method is a robust regression model based on relevance vector machine. The proposed method can reduce the effect of outliers by using a weight strategy. Given a prior distribution of weights, it is shown that the weight values can be determined in a probabilistic way and computed automatically during training. We employ the variational inference method to estimate the posterior distribution over model parameters. Therefore, no validation data set is needed to control the model complexity. That is, the complexity of our proposed method can be self-adjusted in the model training phase. Based on the posterior distribution, we can obtain not only point estimates but useful statistical information such as probabilistic intervals which provide us some useful information about the current status of a manufacturing process. If the actual metrology value falls outside of the intervals, it can be a signal which alerts engineers to the need for preventive maintenance or VM model adjustment. The real plasma etching process of semiconductor manufacturing is presented as a case study to compare the predictive performance of our proposed method with that of conventional VM prediction models. The - xperimental results demonstrate that the proposed method can improve VM prediction accuracy compared to other methods. View full abstract»

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  • A Unified Framework for Outlier Detection in Trace Data Analysis

    Page(s): 95 - 103
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    Process trace data (PTD) is an important data type in semiconductor manufacturing and has a very large aggregate volume. While data mining and statistical analysis play a key role in the quality control of wafers, the existence of outliers adversely affects the applications benefiting from PTD analysis. Due to the complexities of PTD and the resultant outlier patterns, this paper proposes a unified outlier detection framework which takes advantages of data complexity reduction using entropy and abrupt change detection using cumulative sum (CUSUM) method. To meet the practical needs of PTD analysis, a two-step algorithm taking into account of the related domain knowledge is developed, and its effectiveness is validated by using real PTD sets and a production example. The experimental results show that the proposed method outperforms the Fast Greedy Algorithm (FGA) and the Grubb's test, two commonly used outlier detection techniques for univariate data. View full abstract»

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  • Thermal Deformation Prediction in Reticles for Extreme Ultraviolet Lithography Based on a Measurement-Dependent Low-Order Model

    Page(s): 104 - 117
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    In extreme ultraviolet lithography, imaging errors due to thermal deformation of reticles are becoming progressively intolerable as the source power increases. Despite this trend, such errors can be mitigated by adjusting the wafer and reticle stages based on a set of predicted deformation-induced displacements. Since this control scheme operates online, an accurate low-order model is necessary. However, finite element modeling of the reticle and its adjacent components leads to a large-scale thermo-mechanical model that should be simplified. First, parameters of the model's initial thermal condition are reduced to only a few from which numerous initial conditions can be accurately reconstructed. This entails placement of temperature sensors at the corresponding locations, and for this purpose, the discrete empirical interpolation method (DEIM) is utilized. Then, linear and nonlinear model reductions are performed via the proper orthogonal decomposition method and DEIM, respectively. The resultant model is employed in the Kalman filter to estimate the parameters of the reticle's temperature-dependent coefficient of thermal expansion from several displacement measurements and to subsequently predict the displacements that are used for control. By processing the outputs from the simulated large-scale model, this filter is shown to perform successfully, even in the presence of an unexpected initial condition. View full abstract»

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  • Super-Resolving IC Images With an Edge-Preserving Bayesian Framework

    Page(s): 118 - 130
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    Imaging system is one of important components in integrated circuit (IC) packaging, such as flip chip and wafer level packaging. The limit of resolution in the imaging system and the defocus blur by the sensitivity of depth of field, increasingly are the new stumbling block in the pace of package technique keeping up with IC fabrication. The goal of this work is to introduce the potential of image super-resolution (SR) technique in conquering the aforementioned challenges, and facilitates detecting position mark, defect identification and other corresponding post-process applications. An edge-preserving super-resolution Bayesian framework based on total variation regularization is employed. An accurate and efficient motion estimation method is first used to assure the success of SR technique. Mathematically, the convexity of cost function guaranteeing the global optimal solution is demonstrated, and then, the steepest gradient descent for optimizing cost function is reasonably obtained. Eventually, the simulated and real experiments figure out the encouraging performance of the proposed framework that increases certainly the resolution, to the great extent eliminates the defocus blur, and could be considerable robust against the variation of blur and noise level. It is believed that the SR technique for image data processing in the IC package should open a new perspective of coping with technology challenge. View full abstract»

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  • 2014 IEEE Compound Semiconductor IC Symposium (CSICS)

    Page(s): 131
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  • 2014 VLSI Technology Symposuim

    Page(s): 132
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  • IEEE Transactions on Semiconductor Manufacturing information for authors

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
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1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721