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IEEE Design & Test

Issue 6 • Dec. 2013

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Displaying Results 1 - 23 of 23
  • [Front cover]

    Publication Year: 2013, Page(s): C1
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  • [Front inside cover]

    Publication Year: 2013, Page(s): C2
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  • [Masthead]

    Publication Year: 2013, Page(s): 1
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  • Table of contents

    Publication Year: 2013, Page(s): 2
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  • Departments [Table of Contents]

    Publication Year: 2013, Page(s): 3
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  • A Look at Variability and Aging

    Publication Year: 2013, Page(s): 4
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  • Guest Editors' Introduction: Special Issue on Variability and Aging

    Publication Year: 2013, Page(s):5 - 7
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  • Adaptive and Resilient Circuits for Dynamic Variation Tolerance

    Publication Year: 2013, Page(s):8 - 17
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (870 KB) | HTML iconHTML

    This paper focuses on techniques to build more effective circuits for dynamic variation tolerance. Three main approaches are presented based on adaptive circuits, error detection and recovery techniques, and adaptive clock distribution. The tradeoffs in effectiveness and overhead of these different solutions are discussed. View full abstract»

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  • Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology

    Publication Year: 2013, Page(s):18 - 28
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB) | HTML iconHTML

    This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence of statistical variability and reliability impact. As statistical variability sources random discrete dopants, gate-edge roughness, fi-edge roughness, metal-gate granularity and random interface trapped charges in N/PBTI are considered. View full abstract»

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  • Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs

    Publication Year: 2013, Page(s):29 - 39
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1022 KB) | HTML iconHTML

    A set of device-circuit co-design techniques oriented to increase the resilience of FinFET SRAMs circuits is presented in this paper. Co-optimization of fin ratio, thickness, orientation and height are investigated and its impact on performance and area evaluated. View full abstract»

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  • Assessment of Circuit Optimization Techniques Under NBTI

    Publication Year: 2013, Page(s):40 - 49
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB) | HTML iconHTML

    This paper conducts a comprehensive study on existing circuit optimization techniques against NBTI, degradation mechanism that has become a critical reliability issue for nano-scaled IC design. These techniques are categorized by their intrinsic characteristics, and several important observations are made to give design guideline on NBTI mitigation. View full abstract»

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  • Variation and Reliability in FPGAs

    Publication Year: 2013, Page(s):50 - 59
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1115 KB) | HTML iconHTML

    This paper focuses on variability and reliability issues for FPGAs. The paper shows how these issues can be effectively addressed using one of the most powerful features of FPGAs: their ability and flexibility to be reconfigured. The paper also presents techniques for characterizing variability and degradation in these systems. View full abstract»

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  • Debug Automation for Logic Circuits Under Timing Variations

    Publication Year: 2013, Page(s):60 - 69
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (358 KB) | HTML iconHTML

    This paper presents a novel approach to automate speedpath debugging taking into account variations. The proposed technique is based on Boolean Satisfiability. The approach is based on converting the timing behavior of a circuit into the functional domain, inserting a variation logic into the model, and using a Boolean Satisfiability solver to extract failing speedpaths. View full abstract»

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  • Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths

    Publication Year: 2013, Page(s):70 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB) | HTML iconHTML

    The number of open defects in vias has increased with the introduction of the copper process, smaller geometries, and via counts in the order of billions for modern integrated circuits. The authors investigate reliability risks by estimating the Median Time to Failure (MTF) as a function of the void size in vias placed. The number of open defects in vias has increased with the introduction of the ... View full abstract»

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  • Reduced-Code Linearity Testing of Pipeline ADCs

    Publication Year: 2013, Page(s):80 - 88
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1326 KB) | HTML iconHTML

    Pipeline analog-to-digital converters have a repetitive structure, which allows analyzing their static performances by targeting only a small subset of codes. This reduced code testing is an attractive low-cost alternative to the standard techniques based on complete histograms. To guarantee accurate results, the target codes must to be carefully selected, and their measured widths must be appropr... View full abstract»

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  • Single-Event Coupling Soft Errors in Nanoscale CMOS Circuits

    Publication Year: 2013, Page(s):89 - 97
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (529 KB) | HTML iconHTML

    There are various sources of single event transient (SET) errors for combinatorial logic circuits. This article discusses effects of various sources of SET errors and presents a comparative analysis in different technology nodes. View full abstract»

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  • Test Technology TC Newsletter

    Publication Year: 2013, Page(s):98 - 99
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  • IEEE Phaser Data [advertisement]

    Publication Year: 2013, Page(s): 100
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  • CEDA Currents

    Publication Year: 2013, Page(s):101 - 102
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  • IEEE Was Here [advertisement]

    Publication Year: 2013, Page(s): 103
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  • Planned Unobsolescence

    Publication Year: 2013, Page(s): 104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (68 KB) | HTML iconHTML

    Examines the concept of planned obsolescence. View full abstract»

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  • [Back inside cover]

    Publication Year: 2013, Page(s): C3
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  • [Back cover]

    Publication Year: 2013, Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)