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Solid-State Circuits, IEEE Journal of

Issue 2 • Date Feb 1994

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Displaying Results 1 - 14 of 14
  • Comments on the optimum CMOS tapered buffer problem

    Publication Year: 1994 , Page(s): 155 - 158
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    Two recent papers, one by Li et al. (see ibid., vol 25, p1005-8,1990) and the other by Prunty and Gal (see ibid., vol. 27, no. 1, p118-9,1992), on the optimum CMOS tapered buffer problem are commented on. These papers claim that an equivalent “short-circuit” current capacitance should be added to the output capacitance of an inverter to account for the increased propagation delay obtained because of the short-circuit current that flows when a real input waveform is considered instead of an input step voltage. The reasoning results in an optimum tapering factor that is dependent on the waveform rise and fall times. However, the propagation delay only depends on the load capacitance and the ratio of the input to output transition times. In a fixed-taper buffer these transition times are equal making the optimum tapering factor independent of the “short-circuit” current. The comments also suggest an improved method of determining the optimum tapering factor in practical situations based on circuit simulations View full abstract»

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  • Reply to “Comments on the optimum CMOS tapered buffer problem”

    Publication Year: 1994 , Page(s): 158 - 159
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    For original article see ibid., vol 27, p. 118-9 (1992). For comments on original paper see ibid., vol29, no. 2, p155-8 (1994). The optimum tapered buffer has been extensively discussed in the literature. In this correspondence a general model is derived and it is shown that previously reported models are specific cases of the general model presented here View full abstract»

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  • Short channel models and scaling limits of SOI and bulk MOSFETs

    Publication Year: 1994 , Page(s): 122 - 125
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    Analytical device-physics-based models for subthreshold drain current in short channel SOI MOSFETs facilitate accurate and efficient circuit simulation. These models also enable prediction of device scaling limits determined by subthreshold conduction and comparison of these limits with bulk MOSFETs for the same threshold and supply voltages View full abstract»

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  • Simple precision bias circuit for medium-power amplifiers

    Publication Year: 1994 , Page(s): 134 - 137
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    Describes a new bias current regulation circuit for single-stage bipolar and FET amplifiers which achieves high precision and simplicity through a combination of feedback error amplifier with bandgap reference. The internally generated reference voltage can be preset between 100-200 mV. The approach is ideal for applications where the overhead voltage must be minimized to reduce power dissipation, and typically offers <0.5% regulation and ⩽40 ppm/°C temperature coefficient. The authors present three common applications which demonstrate the unique advantages of the new topology View full abstract»

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  • A monolithic GaAs low power L-band successive detection logarithmic amplifier

    Publication Year: 1994 , Page(s): 151 - 154
    Cited by:  Papers (1)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    This paper describes a temperature compensated L-band GaAs MMIC successive detection logarithmic amplifier featuring low power consumption. The amplifier achieved log-linearity of ±2.5 dB and a dynamic range of 60 dB over a 100°C temperature range. This device shows no sacrifice of performance over larger, labor intensive hybrid MIC approaches View full abstract»

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  • A novel approach to controlled programming of tunnel-based floating-gate MOSFETs

    Publication Year: 1994 , Page(s): 147 - 150
    Cited by:  Papers (23)  |  Patents (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    This paper presents a new approach to obtain automatic and accurate control of the threshold voltage of floating-gate MOSFETs programmable by means of tunneling current. The proposed method avoids using a series of partial write/erase operations followed by measurements and adjustment steps, thus achieving a significant advantage in terms of programming time for the same accuracy. The simplicity of the proposed method and its inherent speed make it ideal in a wide range of possible applications View full abstract»

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  • Eliminating inductive noise of external chip interconnections

    Publication Year: 1994 , Page(s): 126 - 129
    Cited by:  Papers (12)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    On-chip balanced drivers can essentially eliminate inductive noise, without any power dissipation penalty, and independently of the number of chip drivers switching simultaneously or the switching speed. In addition, balanced interconnections on PWBs and MCMs substantially reduce crosstalk, increase noise immunity, and eliminate ground noise View full abstract»

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  • An architecture for high-performance/small-area multipliers for use in digital filtering applications

    Publication Year: 1994 , Page(s): 117 - 121
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    A multiplier architecture and encoding scheme well suited for programmable digital filtering applications is described. The multiplier's partial product recoding scheme uses only simple multiplexers and takes advantage of a RAM that stores filter coefficients. We use an optimized 20-transistor full-adder cell in the carry-save adder array, and a carry-select vector-merge adder produces the final output. An integrated circuit comprising an ll-b by ll-b multiplier using second-order recoding has been fabricated in 2-μm CMOS technology. It operates in 22 ns and its core occupies 1.53 mm2. Also, an ll-b by 16-b multiplier using third-order recoding has been fabricated through MOSIS in 1.2-μm CMOS technology. Its core occupies 0.9 mm2 and it operates in 19 ns View full abstract»

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  • A very high-frequency CMOS complementary folded cascode amplifier

    Publication Year: 1994 , Page(s): 130 - 133
    Cited by:  Papers (33)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    A wide-band, fast settling CMOS complementary folded cascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder cascode (FC) or mirrored cascode (MC) approaches for VLSI amplifiers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm2), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a DC gain of approximately 50 dB, with a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF View full abstract»

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  • Electrothermal simulation and design of integrated circuits

    Publication Year: 1994 , Page(s): 143 - 146
    Cited by:  Papers (36)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    An accurate prediction of the electrothermal behavior of power integrated devices is required to design circuits in an efficient way. An electrothermal simulator (ETS) is a combination of SPICE with finite element code, in a relaxation procedure. It simulates the full electrothermal behavior of integrated circuits. Static and dynamic simulations of typical examples, reveal the value of ETS for high-power applications. Some specific design rules are derived. They are simple formulas, which estimate the temperature (gradients) on chip. They can be used before any CPU-time consuming simulation takes place which allows a more efficient design and prototype phase View full abstract»

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  • DC modeling and characterization of AlGaAs/GaAs heterojunction bipolar transistors for high-temperature applications

    Publication Year: 1994 , Page(s): 108 - 116
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    The large signal dc characteristics of AlGaAs/GaAs heterojunction bipolar transistors (HBT) at high temperatures (27°-300°C) are reported. A high-temperature SPICE model is developed which includes the recombination-generation current components and avalanche multiplication which become extremely important at high temperatures. The effect of avalanche breakdown is also included to model the current due to thermal generation of electron/hole pairs causing breakdown at high temperatures. A parameter extraction program is developed and used to extract the model parameters of HBT's at different temperatures. Fitting functions for the model parameters as a function of temperature are developed. These parameters are then used in the SPICE Ebers-Moll model for the dc characterization of the HBT at any temperature between (27°-300°C) View full abstract»

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  • Measurement of MOS current mismatch in the weak inversion region

    Publication Year: 1994 , Page(s): 138 - 142
    Cited by:  Papers (32)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    Measures the current matching properties of MOS transistors operated in the weak inversion region. The authors measured a total of about 1400 PMOS and NMOS transistors produced in four different processes and report the results in terms of mismatch dependance on current density, device dimensions, and substrate voltage, without using any specific model for the transistor View full abstract»

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  • Current-mode CMOS multiple-valued logic circuits

    Publication Year: 1994 , Page(s): 95 - 107
    Cited by:  Papers (39)  |  Patents (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1196 KB)  

    Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described View full abstract»

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  • Novel low-voltage low-power full-swing BiCMOS circuits

    Publication Year: 1994 , Page(s): 86 - 94
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan