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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 2 • Date Feb. 2014

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  • Table of contents

    Publication Year: 2014 , Page(s): C1 - C4
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2014 , Page(s): C2
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  • Delay Test for Diagnosis of Power Switches

    Publication Year: 2014 , Page(s): 197 - 206
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1230 KB) |  | HTML iconHTML  

    Power switches are used as a part of the power-gating technique to reduce the leakage power of a design. To the best of our knowledge, this is the first report in open literature to show a systematic diagnosis method for accurately diagnosing power switches. The proposed diagnosis method utilizes the recently proposed design-for-test solution for efficient testing of power switches in the presence of process, voltage, and temperature variation. It divides power switches into segments such that any faulty power switch is detectable, thereby achieving high diagnosis accuracy. The proposed diagnosis method is validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that, when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; it is less than 12% when considering VT variations. View full abstract»

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  • Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults

    Publication Year: 2014 , Page(s): 207 - 219
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1494 KB) |  | HTML iconHTML  

    3-D integration has been touted as an approach to reducing the lengths of critical paths in field-programmable gate arrays (FPGAs). A 3-D chip stacks a number of 2-D FPGA bare dies, interconnected by through-silicon vias (TSVs) and micro bumps, to attain a high packing density. However, the technology also introduces new types of defects, such as TSV void and microbump misalignment. Testing the interconnection faults becomes inevitable. In this paper, we present an automatic test pattern generator for open, short, and delay faults on 3-D FPGA interconnects by exploiting the regularity of switch matrix topology and forming repetitive paths with finite steps and with loop-back. The experimental results show that 12 test patterns (TPs) suffice to achieve 100% open fault coverage (FC). To detect all possible neighboring short faults, we need more than 40 TPs, whose number increases only slightly with the height of the 3-D FPGA. The TPs have high delay FC (96%) for 3-D FPGAs with the number of configurable logic blocks ranging from 50 × 50 × 2 to 50 × 50 × 6, demonstrating the scalability of our method. View full abstract»

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  • Multivoltage Aware Resistive Open Fault Model

    Publication Year: 2014 , Page(s): 220 - 231
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2541 KB) |  | HTML iconHTML  

    Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs causing delay failures and reliability-related concerns. The widespread utilization of multiple supply voltages in contemporary VLSI designs and emerging test methods poses a critical concern as to whether conventional models for resistive opens will still be effective. Conventional models do not explicitly model the VDD effect on fault behavior and detectability. We have empirically observed that a sensitized ROF could exhibit multiple behaviors across its resistance continuum. We also observe that the detectable resistance range versus VDD varies with test speed. We consequently propose a voltage-aware model that divides the full range of open resistances into continuous behavioral intervals and three detectability ranges. The presented model is expected to substantially enhance multivoltage test generation and fault distinction. View full abstract»

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  • Radiation-Hard Field-Programmable Gate Arrays Configuration Technique Using Silicon on Sapphire

    Publication Year: 2014 , Page(s): 232 - 241
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    Once largely the domain of space-borne applications, the effects of high energy charged particles on electronics systems are now also a concern for conventional terrestrial devices. The configuration memory within reconfigurable components, such as SRAM-based field-programmable gate arrays are particularly vulnerable to radiation-induced single event effects. We present a silicon on insulator (SOI)-based configuration memory system for use in a radiation hard reconfigurable system. A nonvolatile storage cell, able to be manufactured in a standard single polysilicon SOI CMOS process with no special layers, is combined with a Schmitt amplifier, which results in a final structure that exhibits two unique characteristics enhancing its resistance to radiation. First, it is impossible for a radiation-induced event to permanently flip the configuration state. Second, a partial de-programming resulting in a reduction in the magnitude of the storage cell voltage causes a large change in static current that can very easily be detected using a conventional sense amplifier. A simple current detector of the type used in conventional RAM circuits allows the configuration memory to be set up to exhibit self-correcting, or “auto-scrubbing” behavior. Failure estimates indicate a mean time between failures for a single cell to be in the order of 1034 years. View full abstract»

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  • Smart Reliable Network-on-Chip

    Publication Year: 2014 , Page(s): 242 - 255
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2779 KB) |  | HTML iconHTML  

    In this paper, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, we propose online detection of data packet and adaptive routing algorithm errors. Both presented mechanisms are able to distinguish permanent and transient errors and localize accurately the position of the faulty blocks (data bus, input port, output port) in the NoC routers, while preserving the throughput, the network load, and the data packet latency. We provide localization capacity analysis of the presented mechanisms, NoC performance evaluations, and field-programmable gate array synthesis. View full abstract»

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  • Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs

    Publication Year: 2014 , Page(s): 256 - 269
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1434 KB) |  | HTML iconHTML  

    As the feature size shrinks to the nanometer scale, SRAM-based FPGAs will become increasingly vulnerable to soft errors. Existing reliability-oriented placement and routing approaches primarily focus on reducing the fault occurrence probability (node error rate) of soft errors. However, our analysis shows that, besides the fault occurrence probability, the propagation probability (error propagation probability) plays an important role and should be taken into consideration. In this paper, we first propose a cube-based analysis algorithm to efficiently and accurately estimate the error propagation probability. Based on such a model, we propose a novel reliability-oriented placement and routing algorithm that combines both the fault occurrence probability and the error propagation probability together to enhance system-level robustness against soft errors. Experimental results show that, compared with the baseline versatile place and route technique, the proposed scheme can reduce the failure rate by 20.73%, and increase the mean time between failures by 39.44%. View full abstract»

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  • Statistical Framework for Designing On-Chip Thermal Sensing Infrastructure in Nanoscale Systems

    Publication Year: 2014 , Page(s): 270 - 279
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB) |  | HTML iconHTML  

    Thermal/power issues have become increasingly important with more and more transistors being placed on a single chip. Many dynamic thermal/power management techniques have been proposed to address such issues but they all depend heavily on accurate knowledge of the chip's thermal state during runtime. In this paper, we describe a unified statistical framework for designing an on-chip thermal sensing infrastructure that can be used to track the chip's thermal state at runtime. Specifically, we address the following problems in this statistical framework: 1) sensor placement; 2) sensor data compression; 3) sensor data fusion; and 4) overall interplay. Our methods exploit the correlations between temperatures in different parts of the chip to drive sensor placement, data compression, and data fusion in both noiseless and noisy sensor cases. Our framework is also capable of choosing the appropriate degree of compression for each sensor while accounting for their local space constraints during deployment. The experimental results show that the root-mean-square error of the thermal estimates produced by our sensing infrastructure is on average 35% better than an equivalent system that uses a range-based placement scheme and a uniform compression scheme. It took our methods at most about 9 s to decide the overall solution for placement, compression, and data fusion at the design stage. This demonstrates the effectiveness and applicability of our unified statistical design methodology. View full abstract»

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  • Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits

    Publication Year: 2014 , Page(s): 280 - 285
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB) |  | HTML iconHTML  

    This paper presents an extensive statistical study on the impact of bias temperature instability (BTI) on digital circuits. A statistical framework for the evaluation of BTI at the electrical (SPICE) level, enhanced by an atomistic model for BTI, is introduced. This framework is then employed to perform the timing analysis of different combinational paths using cells from a given library, aiming to statistically model BTI at the higher abstraction level. A statistical static timing analysis (SSTA) method is then performed and the results are compared to detailed simulations using atomistic models based on experimental data. The comparison between the two methods shows that for large paths both methods converge to the same distribution for the delay while for short paths the delay distributions are different causing the SSTA method to generate misleading results. An analysis is then performed in order to understand and formalize the results. View full abstract»

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  • Ultra-High Throughput Low-Power Packet Classification

    Publication Year: 2014 , Page(s): 286 - 299
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1062 KB) |  | HTML iconHTML  

    Packet classification is used by networking equipment to sort packets into flows by comparing their headers to a list of rules, with packets placed in the flow determined by the matched rule. A flow is used to decide a packet's priority and the manner in which it is processed. Packet classification is a difficult task due to the fact that all packets must be processed at wire speed and rulesets can contain tens of thousands of rules. The contribution of this paper is a hardware accelerator that can classify up to 433 million packets per second when using rulesets containing tens of thousands of rules with a peak power consumption of only 9.03 W when using a Stratix III field-programmable gate array (FPGA). The hardware accelerator uses a modified version of the HyperCuts packet classification algorithm, with a new pre-cutting process used to reduce the amount of memory needed to save the search structure for large rulesets so that it is small enough to fit in the on-chip memory of an FPGA. The modified algorithm also removes the need for floating point division to be performed when classifying a packet, allowing higher clock speeds and thus obtaining higher throughputs. View full abstract»

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  • Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization

    Publication Year: 2014 , Page(s): 300 - 312
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1482 KB) |  | HTML iconHTML  

    This paper presents a discrete particle swarm optimization (PSO)-based strategy to map applications on both 2-D and 3-D mesh-connected Networks-on-Chip. The basic PSO formulation has been augmented by: 1) running multiple PSOs and 2) deterministically generating a part of the initial population for PSO. The mapping results, in terms of the overall communication metric, have been compared with well-known techniques reported in the literature and also with exact methods built around integer linear programming (ILP). Our PSO-based results are superior to those from reported techniques. For smaller benchmarks, the results obtained are same as those corresponding to the ILP formulation, establishing the quality of the solution strategy. View full abstract»

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  • Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

    Publication Year: 2014 , Page(s): 313 - 321
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2637 KB) |  | HTML iconHTML  

    Radio communication exhibits the highest energy consumption in wireless sensor nodes. Given their limited energy supply from batteries or scavenging, these nodes must trade data communication for on-the-node computation. Currently, they are designed around off-the-shelf low-power microcontrollers. But by employing a more appropriate processing element, the energy consumption can be significantly reduced. This paper describes the design and implementation of the newly proposed folded-tree architecture for on-the-node data processing in wireless sensor networks, using parallel prefix operations and data locality in hardware. Measurements of the silicon implementation show an improvement of 10-20× in terms of energy as compared to traditional modern micro-controllers found in sensor nodes. View full abstract»

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  • Equalization-Based Digital Background Calibration Technique for Pipelined ADCs

    Publication Year: 2014 , Page(s): 322 - 333
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1408 KB) |  | HTML iconHTML  

    In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC. View full abstract»

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  • Time-Based All-Digital Technique for Analog Built-in Self-Test

    Publication Year: 2014 , Page(s): 334 - 342
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2283 KB) |  | HTML iconHTML  

    A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages in an all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of subsampled signals, thus giving rise to as many subsampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding subsampled signal pair is fed to a delay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC 130-nm CMOS process. Sub-millivolt accuracy for static signals is demonstrated for a measurement time of a few seconds, and an effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry. View full abstract»

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  • Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

    Publication Year: 2014 , Page(s): 343 - 352
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1188 KB) |  | HTML iconHTML  

    The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply. View full abstract»

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  • Vector-Matrix Multiply and Winner-Take-All as an Analog Classifier

    Publication Year: 2014 , Page(s): 353 - 361
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1462 KB) |  | HTML iconHTML  

    The vector-matrix multiply and winner-take-all structure is presented as a general-purpose, low-power, compact, programmable classifier architecture that is capable of greater computation than a one-layer neural network, and equivalent to a two-layer perceptron. The classifier generates event outputs and is suitable for integration with event-driven systems. The main sources of mismatch, temperature dependence, and methods for compensation are discussed. We present measured data from simple linear and nonlinear classifier structures on a 0.35-μm chip and analyze the power and computing efficiency for scaled structures. View full abstract»

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  • Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay

    Publication Year: 2014 , Page(s): 362 - 371
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1025 KB) |  | HTML iconHTML  

    In this paper, we present an efficient architecture for the implementation of a delayed least mean square adaptive filter. For achieving lower adaptation-delay and area-delay-power efficient implementation, we use a novel partial product generator and propose a strategy for optimized balanced pipelining across the time-consuming combinational blocks of the structure. From synthesis results, we find that the proposed design offers nearly 17% less area-delay product (ADP) and nearly 14% less energy-delay product (EDP) than the best of the existing systolic structures, on average, for filter lengths N=8, 16, and 32. We propose an efficient fixed-point implementation scheme of the proposed architecture, and derive the expression for steady-state error. We show that the steady-state mean squared error obtained from the analytical result matches with the simulation result. Moreover, we have proposed a bit-level pruning of the proposed architecture, which provides nearly 20% saving in ADP and 9% saving in EDP over the proposed structure before pruning without noticeable degradation of steady-state-error performance. View full abstract»

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  • Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

    Publication Year: 2014 , Page(s): 372 - 383
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6341 KB) |  | HTML iconHTML  

    This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using Vcm-based switching. View full abstract»

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  • Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

    Publication Year: 2014 , Page(s): 384 - 395
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1389 KB) |  | HTML iconHTML  

    The emergence of spin-transfer torque magnetic RAM (STT-MRAM) as a leading candidate for future high-performance nonvolatile memory has led to increased research interest. Current STT-MRAM technology faces several major obstacles in attaining its potential. One of the major issues is in the design of 1T-1MTJ STT-MRAM bit-cells under process variations: the bit-cells need to be significantly upsized to improve bit-cell failure, resulting in increased bit-cell area and power dissipation. In this paper, we analyze four circuit-level solutions that enable smaller 1T-1MTJ STT-MRAM bit-cells with improved yield, namely, bit-line voltage boosting, word-line voltage boosting, access transistor body biasing, and an applied external magnetic field. Results from simulation using 45-nm bulk CMOS access transistor and 40-nm magnetic tunneling junction technology show that word-line voltage boosting can be the best failure mitigation technique. Bit-cells designed with word-line boosting for write has a bit-cell area reduced by > 75% at iso-failure probability, compared to bit-cells without any failure mitigation technique. When bit-cell failure probability is optimized instead, 5 Oe of applied external magnetic field assisted write reduces power consumption by 15% , compared to bit-cells designed without failure mitigation techniques. View full abstract»

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  • Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors

    Publication Year: 2014 , Page(s): 396 - 407
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4073 KB) |  | HTML iconHTML  

    In this paper, we propose a new cache design technique, referred to as early tag access (ETA) cache, to improve the energy efficiency of data caches in embedded processors. The proposed technique performs ETAs to determine the destination ways of memory instructions before the actual cache accesses. It, thus, enables only the destination way to be accessed if a hit occurs during the ETA. The proposed ETA cache can be configured under two operation modes to exploit the tradeoffs between energy efficiency and performance. It is shown that our technique is very effective in reducing the number of ways accessed during cache accesses. This enables significant energy reduction with negligible performance overheads. Simulation results demonstrate that the proposed ETA cache achieves over 52.8% energy reduction on average in the L1 data cache and translation lookaside buffer. Compared with the existing cache design techniques, the ETA cache is more effective in energy reduction while maintaining better performance. View full abstract»

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  • Eliminating Synchronization Latency Using Sequenced Latching

    Publication Year: 2014 , Page(s): 408 - 419
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (594 KB) |  | HTML iconHTML  

    Modern multicore systems have a large number of components operating in different clock domains and communicating through asynchronous interfaces. These interfaces use synchronizer circuits, which guard against metastability failures but introduce latency in processing the asynchronous input. We propose a speculative method that hides synchronization latency by overlapping it with computation cycles. We verify the correctness of our approach through a field programmable gate array implementation and apply it to a number of synthesized benchmarks. Synthesis results reveal that our approach achieves average savings of 135% and 204% in area costs and nearly 100% in power costs compared to two similar speculative techniques. View full abstract»

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  • Monolithic Low-EMI CMOS DC–DC Boost Converter for Portable Applications

    Publication Year: 2014 , Page(s): 420 - 424
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (682 KB) |  | HTML iconHTML  

    This brief presents the design of a novel low-electromagnetic interference DC-DC step-up (boost) switching converter for portable applications. The converter can switch between pulsewidth modulation and pulse-frequency modulation modes for different load conditions, and uses a new ultralow-current spread spectrum frequency modulator to reduce the harmonic noise peak. The stability of the converter system with a spread spectrum frequency modulator is first analyzed in this brief. The harmonic peak reduction for the switching frequency and the second harmonic is 14 and 18 dB, respectively. A new two-stage soft-start circuit is also implemented to greatly reduce the start-up current. The start-up current of the boost converter is effectively limited below 500 mA. This brief also investigates the effects of the spread spectrum on conversion efficiency and output ripple voltage. About 93% maximum conversion efficiency can be reached for both operation modes. The chip was fabricated using a TSMC 2P4M 0.35- μm CMOS process. View full abstract»

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  • Comparative Study of Various Latch-Type Sense Amplifiers

    Publication Year: 2014 , Page(s): 425 - 429
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (602 KB) |  | HTML iconHTML  

    When the input voltage difference of a sense amplifier (SA) exceeds the offset voltage (VOS), the SA correctly detects it and outputs a large signal. However, when the input voltage is in a certain region, the SA can fail to sense the input voltage difference even if it is sufficiently large. This input voltage region is defined as the sensing dead zone of the SA. Because sensing dead zones differ depending on SAs and the input voltages to the SA differ depending on the memory devices, analyzing the sensing dead zone is very important. In this brief, we analyze the sensing dead zones of the most popular latch-type SAs: voltage- and current-latched SAs. Furthermore, a suitable latch-type SA scheme is suggested for various SA input voltages in terms of sensing delay, power consumption, and PDP, using a 65-nm predictive technology model at a VDD of 1.1 V. View full abstract»

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  • Speech Processing on a Reconfigurable Analog Platform

    Publication Year: 2014 , Page(s): 430 - 433
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1269 KB) |  | HTML iconHTML  

    We describe architectures for audio classification front ends on a reconfigurable analog platform. Real-time implementation of audio processing algorithms involving discrete-time signals tend to be power-intensive. We present an alternate continuous-time system implementation of a noise-suppression algorithm on our reconfigurable chip, while detailing the design considerations. We also describe a framework that enables future implementations of other speech processing algorithms, classifier front ends, and hearing aids. View full abstract»

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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu